IP Library Granted Patent US 9,069,685
Granted Patent B2
US 9,069,685 · App. 12/324,927 · Granted Jun 30, 2015

Digital signal processor having instruction set with one or more non-linear functions using reduced look-up table

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Quick Facts
Patent No.
US 9,069,685
App. No.
12/324,927
Granted
Jun 30, 2015
Kind
B2
Abstract

A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values for the non-linear function that are near the value, x, from at least one look-up table, wherein the at least one look-up table stores a subset of values for the non-linear function; and interpolating the two or more obtained values to obtain a result, y. The interpolation may comprise, for example, a linear interpolation or a polynomial interpolation. In a further variation, a modulo arithmetic operation can be employed for a periodic non-linear function.

Claims (34)

1. A method performed by a vector-based digital signal processor for evaluating a non-linear function for a vector, x, comprising:

receiving the vector, x, the vector including scalar values and a parameter for the non-linear function;

in response to a predefined software instruction keyword for said non-linear function, the vector-based digital signal processor processes the scalar numbers simultaneously with the following steps:

invoking at least one hardware non-linear functional unit that implements said non-linear function

obtaining, from at least one look-up table, values for said non-linear function that are near each scalar value of said vector, x, wherein said at least one look-up table includes paired values for said non-linear function; and

interpolating with said paired values to obtain a vector result, y, wherein said predefined software instruction keyword for said non-linear function is part of an instruction set of said vector-based digital signal processor.

2. The method of claim 1 , wherein said interpolating step comprises a linear interpolation.

3. The method of claim 1 , wherein said interpolating step comprises a polynomial interpolation.

4. The method of claim 1 , further comprising a modulo arithmetic operation for a periodic non-linear function.

5. The method of claim 1 , wherein said vector-based digital signal processor executes said predefined software instruction keyword from program code.

6. A vector-based digital signal processor, comprising:

a circuitry to receive a vector that includes a set of scalar numbers and a parameter for a non-linear function;

at least one hardware non-linear functional unit that implements a non-linear function, wherein said hardware non-linear functional unit is invoked by said vector-based digital signal processor in response to a predefined software instruction keyword for said non-linear function, wherein said at least one hardware non-linear functional unit is configured to:

obtain values from at least one look-up table near each scalar number of said vector, x, wherein said at least one look-up table stores a subset of values for said non-linear function; and

interpolate with the values from said at least one look-up table to obtain a vector result, y, wherein said predefined software instruction keyword for said non-linear function is part of an instruction set of said vector-based digital signal processor, wherein the scalar numbers are simultaneously processed by said at least one hardware non-linear functional unit.

7. The vector-based digital signal processor of claim 6 , wherein said at least one hardware non-linear functional unit performs a linear interpolation.

8. The vector-based digital signal processor of claim 6 , wherein said at least one hardware non-linear functional unit performs a polynomial interpolation.

9. The vector-based digital signal processor of claim 6 , further comprising a modulo arithmetic operation for a periodic non-linear function.

10. The vector-based digital signal processor of claim 6 , wherein said vector-based digital signal processor executes said predefined software instruction keyword from program code.

11. An integrated circuit, comprising:

a circuitry arranged to receive a vector, x, including scalar numbers and a parameter for a non-linear function;

a vector-based digital signal processor coupled to the circuitry, the vector-based digital signal processor having:

at least one hardware non-linear functional unit that implements a non-linear function, wherein said hardware non-linear functional unit is invoked by said vector-based digital signal processor in response to a predefined software instruction keyword for said non-linear function, wherein said at least one hardware non-linear functional unit is configured to perform the following steps operations in hardware:

obtain paired values that are near scalar numbers of said vector, x, from at least one look-up table that stores a subset of paired values for a non-linear function; and

interpolate with the paired values obtained from said at least one look-up table to obtain a vector result, y, wherein said predefined software instruction keyword for said non-linear function is part of an instruction set of said vector-based digital signal processor, wherein the scalar numbers are simultaneously processed by said at least one hardware non-linear functional unit.

12. The integrated circuit of claim 11 , wherein said at least one hardware non-linear functional unit performs a linear interpolation.

13. The integrated circuit of claim 11 , wherein said at least one hardware non-linear functional unit performs a polynomial interpolation.

14. The integrated circuit of claim 11 , further comprising a modulo arithmetic operation for a periodic non-linear function.

15. The integrated circuit of claim 11 , wherein said vector-based digital signal processor executes said predefined software instruction keyword from program code.

16. The method of claim 1 , wherein the parameter defines a period for periodic non-linear functions.

17. The method of claim 1 , wherein the parameter includes a value that defines a non-periodic and non-linear function.

18. The vector-based digital signal processor of claim 6 , wherein the parameter for the non-linear function defines a period of a periodic non-linear function.

19. The integrated circuit of claim 11 , wherein the parameter defines a period for periodic non-linear functions.

20. The integrated circuit of claim 11 , wherein the parameter includes a value that defines a non-periodic and non-linear function.

Assignments (7)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 034906/0736 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2014
From: AGERE SYSTEMS LLC
To: LSI CORPORATION
Reel/Frame 034245/0655 →
CERTIFICATE OF CONVERSION Recorded Oct 30, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 034113/0626 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →