Low power vector summation apparatus
View Patent ↗An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
1. A coefficient magnitude detector comprising:
a plurality of XNOR gates for detecting a start of sign extension bits for given coefficients;
a plurality of AND gates for detecting start of sign extension positions of all coefficients in an identified grouping of coefficient taps; and
a leading zero detector for detecting the sign extension position at a highest MSB bit position within the identified grouping of coefficient taps.
2. The coefficient magnitude detector of claim 1 wherein the leading zero detector detects a maximum coefficient magnitude in the identified grouping of coefficient taps and generates a compensation vector corresponding to the detected maximum magnitude.