Block-based crest factor reduction (CFR)
View Patent ↗Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.
1. A block-based crest factor reduction method, comprising:
obtaining a block of data samples comprised of a plurality of samples;
identifying an expanded block having at least one cursor block, the at least one cursor block including at least two pre-cursor blocks and a post-cursor block;
applying said expanded block of data to a crest factor reduction block; and
providing a processed block of data from said crest factor reduction block, the processed block of data excluding the expanded block of data while including modifications to the block of data samples that result from crest factor reduction adjustments in the block of data samples and crest factor reduction adjustments in a first of the at least two pre-cursor blocks.
2. The method of claim 1 , wherein said crest factor reduction block comprises a processor implementing a crest factor reduction algorithm using software instructions.
3. The method of claim 1 , wherein said crest factor reduction block comprises one or more peak detector and pulse cancellers.
4. The method of claim 1 , wherein said method is iteratively performed a plurality of times for said block of data.
5. The method of claim 1 , wherein said crest factor reduction adjustments include a pulse cancellation performed by a vector multiplication and a vector addition.
6. The method of claim 1 , further comprising the step of clipping the processed block of data.
7. The method of claim 1 , wherein a size of the at least one cursor block is approximately half of a cancellation pulse.
8. The method of claim 1 , wherein peaks are cancelled in said block of data samples and in the first of said pre-cursor blocks and not in the post-cursor block.
9. A digital signal processor configured to perform block-based Crest Factor Reduction comprising:
a memory; and
at least one hardware device, coupled to the memory, operative to:
obtain a block of data samples comprised of a plurality of samples;
identify an expanded block having at least one cursor block, the at least one cursor block including at least two pre-cursor blocks and a post-cursor block;
apply said expanded block of data to a crest factor reduction algorithm; and
provide a processed block of data from said crest factor reduction algorithm, the processed block of data excluding the expanded block of data while including modifications to the block of data samples therein that result from adjustments in the block of data samples and adjustments in a first of the at least two pre-cursor blocks.
10. The digital signal processor of claim 9 , wherein said at least one hardware device implements said crest factor reduction algorithm using software instructions.
11. The digital signal processor of claim 9 , wherein said crest factor reduction algorithm employs one or more peak detector and pulse cancellers.
12. The digital signal processor of claim 9 , wherein said method is iteratively performed a plurality of times for said block of data.
13. The digital signal processor of claim 9 , wherein said adjustments include a pulse cancellation performed by a vector multiplication and a vector addition.
14. The digital signal processor of claim 9 , wherein said at least one hardware device is further configured to clip said processed block of data.
15. The digital signal processor of claim 9 , wherein a size of said at least one cursor block is approximately half of a cancellation pulse.
16. The digital signal processor of claim 9 , wherein peaks are cancelled in said block of data samples and in the first of said pre-cursor blocks and no peaks are cancelled in the post-cursor block.
17. A block-based crest factor reduction block, comprising:
an input port to receive a block of data samples comprised of a plurality of samples;
a block-based peak detector and pulse canceller arranged to receive the bock of data samples and to perform said block-based crest factor reduction, the block-based peak detector and pulse canceller responsive to an expanded block having at least one cursor block, the at least one cursor block including at least two pre-cursor blocks and a post-cursor block; and
an output port to provide a processed block of data, wherein the processed block of data includes modifications in the block of data samples that result from adjustments in the block of data samples and adjustments in a first of the at least two pre-cursor blocks while excluding the at least one cursor block.
18. The block-based crest factor reduction block of claim 17 , wherein said block-based crest factor reduction is iteratively performed a plurality of times for said block of data.
19. The block-based crest factor reduction block of claim 17 , wherein said adjustments include a pulse cancellation performed by a vector multiplication and a vector addition.
20. The block-based crest factor reduction block of claim 17 , wherein said adjustments include clipping data samples in the processed block of data.
21. The block-based crest factor reduction block of claim 17 , wherein a size of the said at least one cursor block is approximately half of a cancellation pulse.
22. The block-based crest factor reduction block of claim 17 , wherein peaks are not cancelled in the post-cursor block and are cancelled in said block of data samples and in the first of said pre-cursor blocks.