Patent Assignment
Reel/Frame 035797/0943
Termination and Release of Security Interest in Patents at Reel/Frame No. 32856/0031
Recorded: 2015-05-29
Pages: 22
Assignor
DEUTSCHE BANK AG NEW YORK BRANCH
Executed: 2015-04-20
Assignee
LSI CORPORATION
1320 RIDDER PARK DRIVE, SAN JOSE, CALIFORNIA, 95131
Covered Properties
(105)
Cipher Block Chaining Mode in Encryption/Decryption Processing
Parallelized Dynamic Huffman Decoder
System and Method for Tokening Documents
System and Method of Xml Query Processing
Systems and Methods for Processing Regular Expressions
Parallelized Dynamic Huffman Decoder
Skip Based Control Logic for First in First Out Buffer
Efficient Implementation of Arithmetical Secure Hash Techniques
Architecture and Implementation Method of Programmable Arithmetic Controller for Cryptographic Applications
Digital Signal Processor Having Instruction Set With An Xk Function Using Reduced Look-Up Table
Digital Signal Processor Having Instruction Set With An Exponential Function Using Reduced Look-Up Table
Digital Signal Processor Having Instruction Set With A Logarithm Function Using Reduced Look-Up Table
Systems and Methods for Processing Regular Expressions
Dct-Based Technique with Rhombus Scanning for Image Compression
Low Depth Programmable Priority Encoders
Controller and Method for Statistical Allocation of Multichannel Direct Memory Access Bandwidth
Scalable Packet-Switch
Received Information Monitor Adaptive to Multiple Monitoring Modes in a Communication Device
Adaptive Filtering with Flexible Selection of Algorithm Complexity and Performance
Rapid Sampling Phase Recovery
Bch or Reed-Solomon Decoder with Syndrome Modification
Adaptive Clock Recovery with Step-Delay Pre-Compensation
Three-Stage Architecture for Adaptive Clock Recovery
Windowing Technique for Adaptive Clock Recovery and Other Signal-Processing Applications
Reducing a Degree of a Polynomial in a Polynomial Division Calculation
Impulse Regular Expression Matching
Fully Asynchronous Direct Memory Access Controller and Processor Work
Method and System for Parallel Computation of Linear Sequential Circuits
System and Method for Providing Memory Bandwidth Efficient Correlation Acceleration
Avoiding Stall in Processor Pipeline Upon Read After Write Resource Conflict When Intervening Write Present
Methods and Apparatus for Linked-List Circular Buffer Management
Sequentially packing mask selected bits from plural words in circularly coupled register pair for transferring filled register bits to memory
Copying Data to a Cache Using Direct Memory Access
Low Depth Programmable Priority Encoders
Cache Prefetch Learning
Methods for Efficient State Transition Matrix Based Lfsr Computations
Multi-Destination Direct Memory Access Transfer
Method and Apparatus for Non-uniform Redundancy Packet Error Correction
Time Synchronization Using Packet-Layer and Physical-Layer Protocols
Method and Apparatus for Caching Prefetched Data
Efficient Implementation of M-Algorithm Based on Qr Decomposition for Higher-Order Constellations
Iterative-Division Operations Such as for Header Compression in Packet-Based Communications
Representation of Data Relative to Varying Thresholds
Turbo Parallel Concatenated Convolutional Code Implementation on Multiple-Issue Processor Cores
Motion Estimation for a Video Transcoder
Systems and Methods for Processing Regular Expressions
Time-Domain Acoustic Echo Control
Skip Based Control Logic for First in First Out Buffer
Skip Based Control Logic for First in First Out Buffer
Low Depth Combinational Finite Field Multiplier
Stochastic Vector Based Network Echo Cancellation
Orthogonal Variable Spreading Factor Code Sequence Generation
Methods and Apparatus for Search Sphere Linear Block Decoding
Double Precision Approximation of a Single Precision Operation
Multiplication Dynamic Range Increase by on the Fly Data Scaling
Application:
13/292,377 →
Publication:
US 2013/0113543
Fast Echo Gain Change Detection
Cache Prefetch During Motion Estimation
Implementation of Negation in a Multiplication Operation Without Post-Incrementation
Biquad Infinite Impulse Response System Transformation
Multithreaded DFA architecture for finding rules match by concurrently performing at varying input stream positions and sorting result tokens
BEGIN ANCHOR ANNOTATION IN DFAs
Low Access Time Indirect Memory Accesses
On-Demand Allocation of Cache Memory for Use as a Preset Buffer
Methods and Apparatus for Efficient Tone Detection
Trend-Analysis Scheme for Reliably Reading Data Values from Memory
Method and Apparatus to Perform Floating Point Operations
Adjusting Direct Memory Access Transfers Used in Video Decoding
Efficient Extraction of Execution Sets from Fetch Sets
Controlling a Sequence of Parallel Executions
Application:
13/465,179 →
Publication:
US 2013/0298129
Compiled Control Code Parallelization by Hardware Treatment of Data Dependency
Application:
13/466,389 →
Publication:
US 2013/0305017
Memory Mapped Fetch-Ahead Control for Data Cache Accesses
Application:
13/478,561 →
Publication:
US 2013/0318307
Timestamping Logic with Auto-Adjust for Varying System Frequencies
Patent:
8,598,910 →
Application:
13/565,083 →
Incremental Preamble Detection
Mixed Radix Fast Hadamard Transform for Communication Systems
Architecture and Implementation Method of Programmable Arithmetic Controller for Cryptographic Applications
Application:
13/628,554 →
Publication:
US 2013/0024668
Time Synchronization Using Packet-Layer and Physical-Layer Protocols
Crest Factor Reduction (Cfr) Using Asymmetrical Pulses
Multi-Stage Crest Factor Reduction (Cfr) for Multi-Channel Multi-Standard Radio
Combined Rf Equalizer and I/Q Imbalance Correction
Recursive Digital Pre-Distortion (Dpd)
Method of Concealing Picture Header Errors in Digital Video Decoding
Application:
13/661,675 →
Publication:
US 2014/0119445
COMPLEX NFA STATE MATCHING METHOD THAT MATCHES INPUT SYMBOLS AGAINST CHARACTER CLASSES (CCLs), AND COMPARES SEQUENCE CCLs IN PARALLEL
Dfa-Nfa Hybrid
Dynamic Slice Resizing While Encoding Video
Direct Digital Synthesis Of Signals Using Maximum Likelihood Bit-Stream Encoding
Software Digital Front End (SoftDFE) Signal Processing
Vector Processor Having Instruction Set with Vector Convolution Function for Fir Filtering
Digital Processor Having Instruction Set with Complex Exponential Non-Linear Function
Block-Based Crest Factor Reduction (Cfr)
Non-Deterministic Finite Automaton (Nfa) Overflow Recovery That Ejects an End of Scan Set of Active States into a Buffer
Multi-Layer Approach for Frame-Missing Concealment in a Video Decoder
Multiple Step Non-Deterministic Finite Automaton Matching
Cache Prefetch for Deterministic Finite Automaton Instructions
Dfa Compression and Execution
Efficient Region of Interest Detection
Incremental Dfa Compilation with Single Rule Granularity
Dfa Sub-Scans
Application:
13/755,215 →
Publication:
US 2014/0215090
System and Method for Dfa-Nfa Splitting
System and Method for De-Queuing an Active Queue
Application:
13/795,350 →
Publication:
US 2014/0258759
Transmit Reference Signal Cleanup Within a Synchronous Network Application
Application:
13/796,153 →
Publication:
US 2014/0254735
Preamble Detection Using Vector Processors
Switch Device With Device-Specified Bridge Domains
Application:
13/955,446 →
Publication:
US 2015/0030027
Dynamic Selection of Cache Levels
Application:
13/959,978 →
Publication:
US 2015/0032963
Maximum Likelihood Bit-Stream Generation and Detection Using M-Algorithm and Infinite Impulse Response Filtering
Impulse Regular Expression Matching
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Patent Security Agreement
May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Assignment of Assignor's Interest
Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
Assignment of Assignor's Interest
Mar 23, 2015
From: BALLAPALLE, PRABHAKAR; KUMAR, PHANI U.
To: LSI CORPORATION
Reel/Frame 035233/0388 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031)
Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
Assignment of Assignor's Interest
Feb 8, 2016
From: INTEL CORPORATION
To: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
Reel/Frame 037733/0440 →