Digital signal processor having instruction set with an x
View Patent ↗A digital signal processor is provided having an instruction set with an x K function that uses a reduced look-up table. The disclosed digital signal processor evaluates an x K function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the x K function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.
1. A method performed by a vector-based digital signal processor for evaluating a non-linear x K function for an input vector, x, said method comprising:
obtaining one or more x K software instructions that implement said non-linear x K function;
receiving said input vector comprising at least two scalar numbers and K;
in response to a predefined software instruction keyword for said at least one of said obtained x K software instructions, invoking at least one hardware functional unit that implements said one or more x K software instructions to perform the following steps for each component of said input vector, wherein said vector-based processor processes said at least two scalar numbers of said input vector substantially simultaneously;
computing Log(x) in hardware;
multiplying said Log(x) value by K; and
determining said x K function by applying an exponential function in hardware to a result of said multiplying step, wherein one or more of said computation of Log(x) and said exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input vector, x, wherein said one or more x K software instructions that implement said non-linear x K function is part of an instruction set of said vector-based digital signal processor and wherein said non-linear x K function computes a K th power of said input vector, x.
2. The method of claim 1 , where said Log(x) value is obtained by the input vector, x, to a first part, N, a second part, q, and a remaining part, r, wherein said first part, N, is identified by a position of a most significant bit of said input vector, x, and said second part, q, is comprised of a number of bits following said most significant bit, wherein said number is less than five and small relative to a number of bits in said input vector, x.
3. The method of claim 2 , further comprising the step of obtaining a value
Log
2
(
1
+
1
2
q
)
from a first look-up table based on the second part, q.
4. The method of claim 2 , further comprising the step of computing an epsilon term, ε, using the expression
2
-
N
1
+
1
2
q
r
,
where
(
1
+
1
2
q
)
-
1
is obtained from a look-up table.
5. The method of claim 4 , wherein said epsilon term, ε, is computed by shifting r by N and multiplying by
(
1
+
1
2
q
)
-
1
.
6. The method of claim 4 , further comprising the step of evaluating an expression Log 2 (1+ε) using a polynomial approximation.
7. The method of claim 2 , wherein said logarithm function is determined for the input vector, x, by summing values of N,
Log
2
(
1
+
1
2
q
)
and Log 2 (1+ε) to produce a corresponding component of an output vector.
8. The method of claim 7 , further comprising the step of translating an initial basis for said log(x) function to an arbitrary basis, Y, by multiplying a result of said summing step by Log Y (2), where log Y (2), is obtained from a look-up table.
9. The method of claim 1 , where said exponential function of said result is obtained by decomposing a component of the input vector, x, to an integer part, N, a first fractional part, q 1 , larger than a specified value, x 0 , and a second fractional part, q 2 , smaller than the specified value, x 0 .
10. The method of claim 9 , wherein a value 2 q 2 is computed using a polynomial approximation.
11. The method of claim 9 , wherein a value 2 q 1 is obtained from a look-up table.
12. The method of claim 9 , wherein said exponential function for said result is obtained by multiplying 2 q 2 , 2 q 1 and 2 N together.
13. The method of claim 12 , wherein said multiplication comprises first multiplying the values 2 q 2 and 2 q 1 together and the multiplication by 2 N is performed by shifting a result of the first multiplication by N bits.
14. The method of claim 9 , further comprising the step of converting an initial basis, Z, of the component of the input vector, x, to a desired basis, Y, by multiplying the component of the input vector, x, by log Z (Y), where log Z (Y), is obtained from a look-up table.
15. A vector-based digital signal processor for evaluating a non-linear x K function for an input vector, x, comprising:
a first input for receiving one or more x K software instructions that implement said non-linear x K function;
a data input for receiving said input vector comprising at least two scalar numbers and K;
a set of hardware units responsive to the first input and the data input;
a memory coupled to the hardware units and storing at least one look-up table wherein the vector-based digital signal processor is operative to perform the following steps for each component of said input vector, wherein said vector-based processor processes said at least two scalar numbers of said input vector substantially simultaneously:
in response to a predefined software instruction keyword for said at least one of said received x K software instructions, invoke at least one hardware unit that implements said one or more x K software instructions operative to:
compute Log(x) in hardware;
multiply said Log(x) value by K; and
determine said x K function by applying an exponential function in hardware to a result of said multiplying step, wherein one or more of said computation of Log(x) and said exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input vector, x, wherein said one or more of said x K software instructions that implement said non-linear x K function is part of an instruction set of said digital signal processor and wherein said non-linear x K function computes a K th power of said input vector, x.
16. The vector-based digital signal processor of claim 15 , where said Log(x) value is obtained by decomposing the input vector, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input vector, x, and said second part, q, is comprised of a number of bits following said most significant bit, wherein said number is less than five and small relative to a number of bits in said input vector, x.
17. The vector-based digital signal processor of claim 16 , further configured to obtain a value
Log
2
(
1
+
1
2
q
)
from a first look-up table based on the second part, q.
18. The vector-based digital signal processor of claim 16 , further configured to compute an epsilon term, ε, using the expression
2
-
N
1
+
1
2
q
r
,
where
(
1
+
1
2
q
)
-
1
is obtained from a look-up table.
19. The vector-based digital signal processor of claim 18 , wherein said epsilon term, ε, is computed by shifting r by N and multiplying by
(
1
+
1
2
q
)
-
1
.
20. The vector-based digital signal processor of claim 18 , further configured to compute an expression Log 2 (1+ε) using a polynomial approximation.
21. The vector-based digital signal processor of claim 16 , wherein said logarithm function is determined for the input vector, x, by summing values of N,
Log
2
(
1
+
1
2
q
)
and Log 2 (1+ε) to produce a corresponding component of an output vector.
22. The vector-based digital signal processor of claim 21 , further configured to translate an initial basis for said log(x) function to an arbitrary basis, Y, by multiplying a result of said summing step by Log Y (2), where Log Y (2), is obtained from a look-up table.
23. The vector-based digital signal processor of claim 15 , where said exponential function of said result is obtained by decomposing a component of the input vector, x, to an integer part, N, a first fractional part, q 1 , larger than a specified value, x 0 , and a second fractional part, q 2 , smaller than the specified value, x 0 .
24. The vector-based digital signal processor of claim 23 , wherein a value 2 q 2 is computed using a polynomial approximation.
25. The vector-based digital signal processor of claim 23 , wherein a value 2 q 1 is obtained from a look-up table.
26. The vector-based digital signal processor of claim 23 , wherein said exponential function for said result is obtained by multiplying 2 q 2 , 2 q 1 and 2 N together.
27. The vector-based digital signal processor of claim 26 , wherein said multiplication comprises first multiplying the values 2 q 2 and 2 q 1 together and the multiplication by 2 N is performed by shifting a result of the first multiplication by N bits.
28. The vector-based digital signal processor of claim 23 , further configured to convert an initial basis, Z, of the component of the input vector, x, to a desired basis, Y, by multiplying the component of the input vector, x, by Log Z (Y), where Log Z (Y), is obtained from a look-up table.
29. An integrated circuit, comprising:
a vector-based digital signal processor for evaluating a non-linear x K function for an input vector, x, comprising:
a first input for receiving one or more x K software instructions that implement said non-linear x K function;
a data input for receiving said input vector comprising at least two scalar numbers and K;
a memory storing at least one look-up table; and
at least one processor, coupled to the memory, operative to:
in response to a predefined software instruction keyword for said at least one of said received x K software instructions, invoke at least one hardware functional unit that implements said one or more non-linear x K software instructions operative to perform the following steps for each component of said input vector, wherein said vector-based processor processes said at least two scalar numbers of said input vector substantially simultaneously:
compute Log(x) in hardware;
multiply said Log(x) value by K; and
determine said x K function by applying an exponential function in hardware to a result of said multiplying step, wherein one or more of said computation of Log(x) and said exponential function employ at least one look-up table having entries with a fewer number of bits in the input vector, x, wherein said one or more of said x K software instructions that implement said non-linear x K function is part of an instruction set of said vector-based digital signal processor and wherein said non-linear x K function computes a K th power of said input vector, x.