Avoiding stall in processor pipeline upon read after write resource conflict when intervening write present
View Patent ↗An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.
1. An apparatus comprising:
a processor having a pipeline; and
a circuit configured to (i) detect a first write instruction in said pipeline that writes to a resource, (ii) stall a read instruction in said pipeline where (a) a first read-after-write conflict exists between said first write instruction and said read instruction and (b) no other write instruction to said resource is scheduled between said first write instruction and said read instruction and (iii) not stall said read instruction where (a) said first read-after-write conflict exists and (b) a second write instruction to said resource is scheduled between said first write instruction and said read instruction.
2. The apparatus according to claim 1 , wherein said circuit is further configured to examine a determined number of subsequent instructions scheduled after said first instruction.
3. The apparatus according to claim 2 , wherein said circuit is further configured to cancel said first read-after-write conflict in response to finding said second write instruction among said subsequent instructions.
4. The apparatus according to claim 2 , wherein said determined number matches a stage number in said pipeline where said first instruction writes to said resource.
5. The apparatus according to claim 1 , wherein said second write instruction writes to said resource before said read instruction reads from said resource.
6. The apparatus according to claim 1 , wherein said first write instruction writes to said resource at a particular stage of said pipeline.
7. The apparatus according to claim 6 , wherein (i) said read instruction reads from said resource at a given stage of said pipeline and (ii) said given stage is earlier in said pipeline than said particular stage.
8. The apparatus according to claim 6 , wherein (i) said second write instruction writes to said resource at a given stage of said pipeline and (ii) said given stage is earlier in said pipeline than said particular stage.
9. The apparatus according to claim 1 , wherein said circuit is further configured to check for a second read-after-write conflict between said second write instruction and said read instruction.
10. The apparatus according to claim 1 , wherein said pipeline is an interlocked pipeline.
11. A method for eliminating read-after-write conflicts in a processor, comprising the steps of:
(A) detecting a first write instruction in a pipeline of said processor that writes to a resource;
(B) stalling a read instruction in said pipeline where (i) a first read-after-write conflict exists between said first write instruction and said read instruction and (ii) no other write instruction to said resource is scheduled between said first write instruction and said read instruction; and
(C) not stalling said read instruction where (i) said first read-after-write conflict exists and (ii) a second write instruction to said resource is scheduled between said first write instruction and said read instruction.
12. The method according to claim 11 , further comprising the step of:
examining a determined number of subsequent instructions scheduled after said first instruction.
13. The method according to claim 12 , further comprising the step of
canceling said first read-after-write conflict in response to finding said second write instruction among said subsequent instructions.
14. The method according to claim 12 , wherein said determined number matches a stage number in said pipeline where said first instruction writes to said resource.
15. The method according to claim 11 , wherein said second write instruction writes to said resource before said read instruction reads from said resource.
16. The method according to claim 11 , wherein said first write instruction writes to said resource at a particular stage of said pipeline.
17. The method according to claim 16 , wherein (i) said read instruction reads from said resource at a given stage of said pipeline and (ii) said given stage is earlier in said pipeline than said particular stage.
18. The method according to claim 16 , wherein (i) said second write instruction writes to said resource at a given stage of said pipeline and (ii) said given stage is earlier in said pipeline than said particular stage.
19. The method according to claim 11 , further comprising the step of:
checking for a second read-after-write conflict between said second write instruction and said read instruction.
20. A method for eliminating read-after-write conflicts in a processor, comprising the steps of:
(A) detecting a first write instruction schedule in a pipeline of said processor that writes to a resource;
(B) inserting one or more no-operation instructions before a read instruction where (i) a first read-after-write conflict exists between said first write instruction and said read instruction and (ii) no other write instruction to said resource is scheduled between said first write instruction and said read instruction; and
(C) not inserting said no-operation instructions before said read instruction where (i) said first read-after-write conflict exists and (ii) a second write instruction to said resource is scheduled between said first write instruction and said read instruction.