Patent Assignment
Reel/Frame 037733/0440
Assignment of Assignor's Interest
Recorded: 2016-02-08
Pages: 20
Assignor
INTEL CORPORATION
Executed: 2016-02-04
Assignee
BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
THE RAINBOW CITY OFFICE BUILDING, 68 QINGHE MIDDLE STREET HAIDIAN DISTRICT, BEIJING, 100085, CHINA
Covered Properties
(332)
Memory Based Vlsi Architecture for Image Compression
Patent:
6,694,061 →
Application:
08/885,415 →
Integrated Cmos Imager
Patent:
6,747,695 →
Application:
08/985,838 →
Method and Apparatus for Controlling Bus Transactions Depending on Bus Clock Frequency
Patent:
7,363,401 →
Application:
08/990,420 →
A Field Effect Transistor
Patent:
6,707,120 →
Application:
09/097,991 →
Digital Content Protection Using a Secure Booting Method and Apparatus
Patent:
6,735,696 →
Application:
09/133,979 →
Metal to Ild Adhesion Improvement by Reactive Sputtering
Patent:
6,746,727 →
Application:
09/139,286 →
Method and Apparatus for Controlling a Test Cell
Patent:
6,732,053 →
Application:
09/164,073 →
Insulated Channel Field Effect Transistor with an Electric Field Terminal Region
Personal Computer-Based Paging System
Implementing Termination with a Default Signal on a Bus Line
Method and Apparatus for Conserving Power Consumed by a Network Interface Device in Packet Filtering Mode
Patent:
6,732,190 →
Application:
09/265,033 →
Multimedia Data Delivery and Playback System with Multi-Level Content and Privacy Protection
Patent:
6,668,246 →
Application:
09/275,905 →
Ceric-Ion Slurry for Use in Chemical-Mechanical Polishing
Dc-To-Dc Converter
Patent:
6,704,211 →
Application:
09/289,420 →
Method of Distributed Resource Management of I/O Devices in a Network Cluster
Patent:
6,732,166 →
Application:
09/322,183 →
Internal Processor Buffering for Implicit Writebacks
Transistor Structure Having Silicide Soure/Drain Extensions
Secure Packet Processor
Patent:
6,725,371 →
Application:
09/345,683 →
Amplifier Assisted Active Pixel Read Out Structure
Patent:
6,717,616 →
Application:
09/374,815 →
Networking Method and Apparatus Using Silent Slots to Facilitate Transmission Collision Detection
Patent:
6,765,924 →
Application:
09/378,555 →
Kernel Interface
Patent:
6,742,051 →
Application:
09/386,517 →
Method and System for Diagnosing Network Intrusion
Patent:
6,735,702 →
Application:
09/386,586 →
Apparatus and Method for Dynamic Resource Allocation in a Network Environment
Patent:
6,771,595 →
Application:
09/387,077 →
Methods and Apparatus for Selecting Wire Video Size
Patent:
6,731,325 →
Application:
09/392,103 →
Multiplexer Selecting One of Input/Output Data from a Low Pin Count Interface and a Program Information to Update a Firmware Device from a Communication Interface
Intergrated Circuit Test Probe Having Ridge Contact
Using Video Information to Control Cursor Position
Method for Specifying Tcp/Ip Packet Classification Parameters
Patent:
6,728,243 →
Application:
09/430,674 →
Method and Apparatus for Making and Using a Beacon Fiducial for an Integrated Circuit
Patent:
6,753,541 →
Application:
09/451,471 →
Rendering a Two-Dimensional Image
Patent:
6,762,759 →
Application:
09/454,504 →
Signal Repeater for Voltage Intolerant Components Used in a Serial Data Line
Patent:
6,744,810 →
Application:
09/459,744 →
System and Method for Safeguarding Data Within a Device
Patent:
6,668,324 →
Application:
09/460,537 →
Electrically Modifiable Product Labeling
Patent:
6,731,221 →
Application:
09/467,735 →
Method and Apparatus for Coordinating Cooperating Resources and Its Application
Patent:
6,715,009 →
Application:
09/468,479 →
Detecting Defects on Photomasks
Patent:
6,701,004 →
Application:
09/470,082 →
Method and Apparatus for Performing a Vertical Scale Filter Function in a Graphics Device Using a Single Line Buffer
Patent:
6,710,784 →
Application:
09/470,101 →
Single Array Banked Branch Target Buffer
Method and Apparatus for Testing an Integrated Circuit Having an Output-to-Output Relative Signal
Patent:
6,693,436 →
Application:
09/471,638 →
Centralized Technique for Assigning I/O Controllers to Hosts in a Cluster
Patent:
6,738,818 →
Application:
09/472,445 →
Testing for Digital Signaling
Patent:
6,704,277 →
Application:
09/474,564 →
Method and Apparatus for Scan Design Using a Formal Verification-Based Process
Patent:
6,748,352 →
Application:
09/474,942 →
Method and Apparatus for Remote Memory Clock Synchronization for Optimized Leadoff Performance
Patent:
6,771,669 →
Application:
09/475,458 →
Controlled Potential Anodic Etching Process for the Selective Removal of Conductive Thin Films
Integration of Annealing Capability into Metal Deposition or Cmp Tool
Patent:
6,730,598 →
Application:
09/475,729 →
Fast Branch Misprediction Recovery Method and System for a Computer Architecture
Patent:
6,757,816 →
Application:
09/476,227 →
Method and Apparatus for Routing Using Deferred Merging
Patent:
6,766,502 →
Application:
09/476,416 →
Upgrading an Integrated Graphics Subsystem
Patent:
6,760,031 →
Application:
09/476,658 →
Interface for Performing Motion Compensation
Patent:
6,707,853 →
Application:
09/481,374 →
Block-Oriented Pixel Filter
Patent:
6,711,301 →
Application:
09/494,745 →
Method and Apparatus for Achieving Architectural Correctness in a Multi-Mode Processor Providing Floating-Point Support
Remote Control of a Linked Computer
Patent:
6,748,423 →
Application:
09/513,008 →
Self Correcting Server Which Retries Automatic Body Error Recovery Before Seeking Remote Assistance
Patent:
6,763,456 →
Application:
09/514,849 →
Transfer of Information Between Devices on Different Buses
Patent:
6,754,759 →
Application:
09/520,802 →
Function Modification in a Write-Protected Operating System
Patent:
6,718,414 →
Application:
09/521,677 →
System and Method to Generate a Float Voltage Potential at Output When First and Second Power Supplies Fail to Supply Power at the Same Time
Patent:
6,647,500 →
Application:
09/524,102 →
Cellular Telephone Docking System
Patent:
6,704,580 →
Application:
09/524,715 →
Work Queue Alias System and Method Allowing Fabric Management Packets on All Ports of a Cluster Adapter
Patent:
6,741,602 →
Application:
09/538,263 →
Managing Resources in a Bus Bridge
Patent:
6,708,240 →
Application:
09/538,953 →
System and Method of Using Partially Resolved Predicates for Elimination of Comparison Instruction
Patent:
6,732,356 →
Application:
09/540,145 →
Method and System for Handling Proprietary Protocols and Transmission Control Protocol/Internet Protocol (Tcp/Ip) Over a Point-to-Point (Ppp) Connection
Patent:
6,760,329 →
Application:
09/540,548 →
Method and Apparatus for Image Segmentation
Patent:
6,707,940 →
Application:
09/541,061 →
System for Rearranging Plurality of Memory Storage Elements in a Computer Process to Differrent Configuration Upon Entry into a Low Power Mode of Operation
Patent:
6,715,091 →
Application:
09/546,096 →
Automated Clock Alignment for Testing Processors in a Bypass Mode
Patent:
6,704,892 →
Application:
09/583,268 →
Method and Apparatus for Determining Points of Interest on an Image of a Camera Calibration Object
Patent:
6,768,509 →
Application:
09/592,071 →
Method and Apparatus for Enabling a Wake-Up Event by Modifying a Second Register to Enable a Second Wake-Up Event Responsive to Detecting Entry of Data in a First Register
Patent:
6,725,384 →
Application:
09/607,335 →
Symmetric Voltage Follower Buffer
Patent:
6,717,445 →
Application:
09/608,086 →
Integrated Signaling / Payload Cross Connect Architecture
Patent:
6,707,816 →
Application:
09/608,353 →
Apparatus and Method for Obtaining Geographical Information Using a Touch-Senstive Globe Device
Patent:
6,720,956 →
Application:
09/608,646 →
System and Method for Reducing Over-Shoot and Ringback by Delaying Input and Establllishing a Synchronized Pulse Over Which Clamping Is Applied
Patent:
6,694,444 →
Application:
09/608,719 →
Lazy Symbolic Model Checking
Patent:
6,725,431 →
Application:
09/608,746 →
Forwarding Data in a Routing Architecture
Patent:
7,366,186 →
Application:
09/608,997 →
Method and System for Training of a Classifier
Patent:
6,728,674 →
Application:
09/629,704 →
Memory Programming Method and System
Patent:
6,687,496 →
Application:
09/631,871 →
Arrangements for Out-of-Order Queue Cache Coherency and Memory Write Starvation Prevention
Patent:
6,738,869 →
Application:
09/649,513 →
Checking Events Generated by a Device
Patent:
6,751,752 →
Application:
09/654,443 →
Dynamically Configurable Clocking Scheme for Demand Based Resource Sharing with Multiple Clock Crossing Domains
Patent:
6,735,712 →
Application:
09/657,559 →
Method and Apparatus for Dynamic Mirroring Availability in a Network Appliance
Patent:
6,757,841 →
Application:
09/662,100 →
Method and Apparatus for Minimizing Bus Contention for I/O Controller Read Operations
Patent:
6,721,835 →
Application:
09/663,953 →
Method for Hibernation of Host Channel Adaptors in a Cluster
Patent:
6,725,386 →
Application:
09/666,595 →
Multiple Non-Contiguous Block Erase in Flash Memory
Patent:
6,748,482 →
Application:
09/670,849 →
Critical Loads Guided Data Prefetching
Patent:
6,760,816 →
Application:
09/675,713 →
3D Encoder
Patent:
6,700,563 →
Application:
09/676,027 →
System for Generating Speech and Non-Speech Audio Messages
Patent:
6,760,704 →
Application:
09/676,104 →
Symbolic Model Checking with Dynamic Model Pruning
Patent:
6,643,827 →
Application:
09/677,262 →
Die-In Heat Spreader Microelectric Package
Patent:
6,709,898 →
Application:
09/679,733 →
Glitch Detection Circuit for Outputting a Signal Indicative of a Glitch on a Strobe Signal and Initializing an Edge Detection Circuit in Response to a Control Signal
Patent:
6,745,337 →
Application:
09/690,118 →
Supply Noise Filter for Clock Generator
Patent:
6,714,092 →
Application:
09/703,723 →
Method and Apparatus for Detecting Defects in a Circuit Using Spectral Analysis of Transient Power Supply Voltage
Patent:
6,717,428 →
Application:
09/705,073 →
Coherent Light Despeckling
Patent:
6,738,105 →
Application:
09/706,494 →
High Speed Computer Bus System with Bi-Directional Transmission Medium and Interface Device
Patent:
6,654,846 →
Application:
09/712,326 →
Electrostatic Discharge Compatible Voltage Reference Buffer
Patent:
6,654,214 →
Application:
09/721,554 →
A Computer Assembly with Stub Traces Coupled to Vias to Add Capacitance at the Vias
Patent:
6,708,243 →
Application:
09/724,634 →
High Speed Vlsi Digital Tester Architecture for Real-Time Output Timing Acquisition, Results Accumulation, and Analysis
Joint Test Action Group (Jtag) Tester, Such as to Test Integrated Circuits in Parallel
Pipelined Compressor Circuit
Method and Apparatus for a Tracking Data Receiver Compensating for Deterministic Jitter
Obtaining a High Refresh Rate Display Using a Low Bandwidth Digital Interface
Method and Apparatus for Performing Subtraction in Redundant Form Arithmetic
Method and Apparatus for Controlling a Multi-Mode I/O Interface
Method and Apparatus for Detecting Strobe Errors
Method and Apparatus for Dynamic Processor Configuration by Limiting a Processor Array Pointer
Method of Determining Non-Accessible Device I/O Pin Speed Using on Chip Lfsr and Misr as Data Source and Results Analyzer Respectively
Configuring Computer Components
Wireless Display Systems, Styll, and Associated Methods
Decoder-Based Circuitry for Sharing an Interrupt Between Disk Drive Interfaces
Method and Apparatus for Pulse Template Matching
Entering and Exiting Power Managed States Without Disrupting Accelerated Graphics Port Transactions
Method, Apparatus, and Machine-Readable Medium to Enhance Microprocessor Performance
Look-Up Table Based Circuitry for Sharing an Interrupt Between Disk Drive Interfaces
Efficient Multiple Power and Ground Distribution of Smt Ic Packages
Managing Access to a Network
Method and Apparatus for Failure Detection Utilizing Functional Test Vectors and Scan Mode
Pseudo Static Memory Cell for Digital Light Modulator
Modifying a Relational Database
Method and Apparatus to Calculate the Difference of Two Numbers
Checkerboard Parity Techniques for a Multi-Pumped Bus
Synchronous Clock Generator for Integrated Circuits
Method and Apparatus for Sliding Window Link Physical Error Detection
Docking Digital Picture Displays
Stiffening Flat-Panel Displays
Apparatus and Method for Enhanced Channel Adapter Performance Through Implementation of a Completion Queue Engine and Address Translation Engine
Method and Apparatus for Handling Ordered Transactions
Patent:
6,754,751 →
Application:
09/821,085 →
Method and System of Controlling Dynamically Compiled Native Code Size
Mechanism for Tracking Colored Objects in a Video Sequence
Buried Intersignal Capacitance
Split Delay Transmission Line
Patent:
6,711,640 →
Application:
09/823,147 →
Amplification Control Scheme for a Receiver
Patent:
6,771,720 →
Application:
09/823,488 →
Memory Addressing Structural Test
Personal Audio Device with Touch Operator
Method and Apparatus for Fault Tolerant and Flexible Test Signature Generator
Method and Apparatus for Communicating with Plug and Play Devices
Reusable Thermal Solution Attachment Mechanism and Methods of Using Same
Computer System and Method of Computer Initialization with Caching of Option Bios
Tag Design for Cache Access with Redundant-Form Address
Method and Apparatus for Text Image Stretching
Patent:
7,348,983 →
Application:
09/888,128 →
Electronic Assembly with Separate Power and Signal Connections
Throttling Queue
System and Method for Device Support
Body Bias Using Scan Chains
Carousel Exhibiting Multiple Occurrences of a Module
Method and Apparatus for High Throughput Short Packet Transfers with Minimum Memory Footprint
Method and Apparatus for Sen-Ref Equalization
Delivering Calls Using Calendar Information
Processing Relatively Thin Glass Sheets
Facilitating the Spread of Encapsulant Between Surfaces of Elecronic Devices
Information Retrieval Center Gateway
Configurable Power Distribution Circuit
Creating a Cutting Template for a Virtual Jigsaw Puzzle Using Guide Points and a Spline-Fitting Algorithm
Manufacturing Process for a Radial Fin Heat Sink
Contact Array for Semiconductor Package
Iodine-Containing Thermal Interface Material
Efficient Termination for Wound Capacitors
Methods to Compensate for Stress Between Heat Spreader and Thermal Interface Material
Noise and Power Optimization in High Performance Circuits
Memory Access Latency Hiding with Hint Buffer
Local Bus Polling Support Buffer
Method and Apparatus for Per-Call Filtering of H.323 Packets
Method and Apparatus for Adaptive Handwriting Teaching System
Display Panel
Methods of Hierarchical Static Scene Simplification and Polygon Budgeting for 3D Models
Patent:
6,765,574 →
Application:
09/979,630 →
Hole Grid Array Package and Socket Technology
Regulating File System Device Access
Integrated Circuit Current Reference
Method of Treating an Electroless Plating Waste
Electronic Package Design with Improved Power Delivery Performance
Command Ordering
Method for Implementing Dual Link List Structure to Enable Fast Link-List Pointer Updates
Low Clock Swing Latch for Dual-Supply Voltage Design
Impedance Compensation for Circuit Board Breakout Region
Computer System Which Locks a Server Unit Subassembly in a Selected Position in a Support Frame
Repeatable Swizzling Patterns for Capacitive and Inductive Noise Cancellation
Weak Current Generation
Plane Splits Filled with Lossy Materials
Method and Apparatus for Improving Digital Circuit Design
Utilizing Overhead in Fixed Length Memory Block Pools
Plasma Etching Uniformity Control
Thermal Solution for a Mezzanine Card
Low Cost High Speed Board-to-Board Coaxial Connector Design with Co-Planar Waveguide for Pcb Launch
Stacked Dice Standoffs
Low Power Entry Latch to Interface Static Logic with Dynamic Logic
Methods and Apparatuses of Presenting Categorical Programs in Progressive Levels of Content Details
Apparatus and Method for Interconnection Between a Component and a Printed Circuit Board
Dual Bus Memory Controller
Cooling Method and Apparatus for Handheld Devices
System, Protocol and Related Methods for Providing Secure Manageability
Individual Memory Page Activity Timing Method and System
Semiconductor Package with Integrated Conical Vapor Chamber
Surface Mount Socket Contact Providing Uniform Solder Ball Loading and Method
Decision Feedback Equalization Employing a Lookup Table
Method and System for Synchronizing a Quadrature Amplitude Modulation Demodulator
Method for Dynamically Adding New Code to an Application Program
Apparatus and Method for Simd Modular Multiplication
Method and Apparatus for Semiconductor-Based Integrated Polarization Modulator/Compensator
Zero Insertion Force Heat-Activated Retention Pin
Static, Low-Voltage Fuse-Based Cell with High-Voltage Programming
Retainer for Circuit Board Assembly and Method for Using the Same
Method of Making a Semiconductor Device That Includes a Dual Damascene Interconnect
Accelerated Visualization of Surface Light Fields
Dynamically Reconfiguring Clock Domains on a Chip
Selective Assembly Loading and Execution Based on Platform Capabilities
Semiconductor Controlled Rectifier / Semiconductor Controlled Switch Based Esd Power Supply Clamp with Active Bias Timer Circuitry
Flip-Flop Circuit
Add-In Card Edge-Finger Design/Stackup to Optimize Connector Performance
Vcc Adaptive Dynamically Variable Frequency Clock System for High Performance Low Power Microprocessors
Circuits and Methods for Selectively Latching the Output of an Adder
Method and Apparatus of Stage Amplifier of Analog to Digital Converter
Enabling an Interim Density for Top Boot Flash Memories
Device Testing
Power System Including Redundant Power Supplies
Methods and Apparatus for Optimizing the Operating Speed and Size of a Computer Program
Low Frequency Testing, Leakage Control, and Burn-in Control for High-Performance Digital Circuits
Communication System and Method for Communicating Frames of Management Information in a Multi-Station Network
Method and Apparatus for Providing Discrete Data Storage Security
Booster Lens for a Microscope
Using Sonic Energy in Connection with Laser-Assisted Direct Imprinting
Flexible Head Probe for Sort Interface Units
Efficient, Table-Driven, Integer-Based Method for Approximating Down Sampling of Wave Data
Semiconductor-On-Insulator Resistor-Capacitor Circuit
High-Power Double Throw Lever Zip Socket
Apparatus and Method to Retain an Electronic Component in a Precise Position During Assembly Manufacturing
Patent:
6,700,782 →
Application:
10/306,355 →
Method, System, and Article of Manufacture for Increasing Network Throughput
Circuit to Extract Nonadjacent Bits from Data Packets
Method and Apparatus for Measuring Thread Wait Time
Dynamic Cmos Circuits with Individually Adjustable Noise Immunity
Memory Cell Leakage Reduction
Patent:
6,724,649 →
Application:
10/324,178 →
Communicating Information Using a Configurable Protocol
Analog Filter Architecture
Switchable Voltage Clamp Circuit
High Performance Euv Mask
Support of Dual Infrared Remote Signaling Protocols
Phase/Frequency Detector for Tracking Receivers
Variable Pad Diameter on the Land Side for Improving the Co-Planarity of Ball Grid Array Packages
Patent:
6,750,549 →
Application:
10/335,202 →
Retention Mechanism for an Electrical Assembly
Switch and/or Router Unit
Euv Mask Blank Defect Mitigation
Method and Apparatus for Cooling an Electronic Component
Patent:
6,771,508 →
Application:
10/367,239 →
Method and System for Label-Based Packet Forwarding Among Multiple Forwarding Elements
Apparatus and a Method for Pmos Drain Current Degradation Compensation
Patent:
6,768,351 →
Application:
10/400,978 →
Inlining with Stack Trace Cache-Based Dynamic Profiling
Enhanced Inspection of Extreme Ultraviolet Mask
Reclaiming Virgin Test Wafers
Patent:
6,761,625 →
Application:
10/441,448 →
Packet Processing System
Threshold Voltage Compensation
Patent:
6,768,369 →
Application:
10/448,304 →
Selectively Activating Display Column Sections
Thermal Interface Apparatus, Systems, and Methods
Output Signal Control from a Dac-Driven Amplifier-Based Driver
Method and Apparatus to Extract Integer and Fractional Components from Floating-Point Data
System and Method for Efficient Hardware Implementation of a Perfect Precision Blending Function
Support for Non-Standard Device Containing Operating System Data
Method, Apparatus and System for Optimizing Routing of Mobile Ip Packets
Platform and Method for Establishing Trust Without Revealing Identity
Processor with Multiple Linked List Storage Feature
Access Point Association History in Wireless Networks
Power and Data Rate Control in a Multi-Rate Wireless System
Patent:
7,346,364 →
Application:
10/696,687 →
Method for Increasing Ferroelectric Characteristics of Polymer Memory Cells
Poisoned Error Signaling for Proactive Os Recovery
Low Cost Compliance Test System and Method
Transmit Scheduling Supporting Temporarily Unavailable Receivers
Trellis Decoder and Method of Decoding
Method and System for Synchronizing Platform Clocks in a Distributed Wireless Platform
Color Distribution for Texture and Image Compression
Computation of All-Pairs Reaching Probabilities in Software Systems
Method and Apparatus to Support Remote Configuration Code
Methods and Apparatus for Merging Critical Sections
Integrated Circuit and Methods for Third Sub Harmonic Up Conversion and Down Conversion of Signals
Apparatus to Compensate for Stress Between Heat Spreader and Thermal Interface Material
Method and Apparatus of Bandwidth Indicator
Method and Apparatus for Testing a Memory Array
Variable Optical Attenuator Multiplexer with a Thermal Isolating Optical Joint
Virtual Firmware Smart Card
Method and Apparatus to Preserve a Hash Value of an Executable Module
Interconnects with Direct Metalization and Conductive Polymer
Methods and Apparatus for Testing Circuit Boards
Multi-Version Register File for Multithreading Processors with Live-in Precomputation
Method, System, and Apparatus for Loopback Entry and Exit
Engine for Comparing a Key with Rules Having High and Low Values Defining a Range
Waveguide Coupling Mechanism
Array Capacitor with Resistive Structure
Method, Apparatus and System for Dynamically Allocating Sequestered Computing Resources
Automatic Generation of Software-Controlled Caching and Ordered Synchronization
Method to Provide Autonomic Boot Recovery
Method and System for Testing Distributed Logic Circuitry
Method and Apparatus to Enhance Platform Boot Efficiency
Enforcing Global Ordering Through a Caching Bridge in a Multicore Multiprocessor System
Method, System, and Program for Addressing Pages of Memory by an I/O Device
Method and Apparatus for Providing a Control Frame Duration Correlated to Data Frame Duration
Delamination Reduction Between Vias and Conductive Pads
Cache Eviction Technique for Reducing Cache Eviction Traffic
Shock Absorbing System for Circuit Boards
Method and Apparatus for Animation of a Human Speaker
Method and Apparatus for Managing Virtual Addresses
Methods and Apparatus for Providing a Radio Frequency Identification System
Method of Bonding a Microelectronic Die to a Substrate and Arrangement to Carry Out Method
Buffer Allocation for Split Data Messages
Reservation with Access Points
Techniques for Password Attack Mitigation
Parallel Test Mode for Multi-Core Processors
Memory Protection Within a Virtual Partition
Dynamic Offset Compensation Based on False Transitions
Amine-Free Deposition of Metal-Nitride Films
Dynamic Detection of Block Boundaries on Memory Reads
Lock-Free Bounded Fifo Queue Mechanism
Processor with Flexible Clock Configuaration
Wireless Communication Device and Method for Dynamic Bidirectional Aggregation of Mac Frames with Delayed Channel Access in a Wireless Network
Apparatus and System for an Ic Substrate, Socket, and Assembly
Mechanism for Read-Only Memory Built-in Self-Test
Battery Level Based Configuration of a Mobile Station by a Base Station
Automated Analysis System for Semiconductor Manufacturing Fabrication
Monolithic Active Optical Cable Assembly for Data Device Applications and Various Connector Types
Chase Algorithm Based Differential Decoder for Soft Decision Reed Solomon Decoding in a Qam System
Maintaining Convergence of a Receiver During Changing Conditions
Signal Compression for Fiber Node
Method and Apparatus for Frame Control Header Decoding Using Cyclic Shifting of Bits
Wireless Data Transmission Methods, Devices, and Systems
Method and Apparatus for Obtaining and Processing Image Features
Geographical Scheduling and Association Procedure for Wimax Systems
Probing Analog Signals
Techniques to Determine Transmitter Power
Mimo Symbol Decoder and Method for Decoding Spatially Multiplexed Symbols Using Combined Linear Equalization and Maximum Likelihood Decoding
Branch Target Buffer with Entry Source Field for Use in Determining Replacement Priority
Low Depth Programmable Priority Encoders
Windowing Technique for Adaptive Clock Recovery and Other Signal-Processing Applications
Fully Asynchronous Direct Memory Access Controller and Processor Work
Method and System for Parallel Computation of Linear Sequential Circuits
System and Method for Providing Memory Bandwidth Efficient Correlation Acceleration
Avoiding Stall in Processor Pipeline Upon Read After Write Resource Conflict When Intervening Write Present
Multi-Destination Direct Memory Access Transfer
Method and Apparatus for Caching Prefetched Data
Efficient Implementation of M-Algorithm Based on Qr Decomposition for Higher-Order Constellations
Representation of Data Relative to Varying Thresholds
Cache Replacement Using Active Cache Line Counters
On-Demand Allocation of Cache Memory for Use as a Preset Buffer