Method and apparatus for managing virtual addresses
View Patent ↗A method for managing virtual memory addresses includes associating a guest identifier (ID) with a virtual machine accessing a virtual memory address. A physical memory address is retrieved corresponding to the virtual memory address utilizing the guest ID. Other embodiments are described and claimed.
1. A method for managing virtual memory addresses, comprising:
associating a guest identifier (ID) with a virtual machine (VM) accessing a virtual memory address;
retrieving a physical memory address by referencing an entry on a table associated with the guest ID; and
intercepting a call to return a size of a region ID and to return a value smaller than a supported size, wherein intercepting the call includes protecting an entry point of a Protection Abstraction Layer.
2. The method of claim 1 , wherein retrieving the physical memory address comprises referencing the entry on the table associated with the guest ID, a region ID, and a virtual page number associated with the virtual memory address.
3. The method of claim 2 , wherein the table resides in a translation look-aside buffer (TLB).
4. The method of claim 1 , further comprising determining a region ID assigned to a virtual region corresponding to a virtual region number in the virtual memory address.
5. The method of claim 4 , wherein determining the region ID comprises reading a region register associated with a virtual region corresponding to the virtual region number.
6. The method of claim 1 , further comprising reading the guest ID from a region register associated with a virtual region corresponding to a virtual region number in the virtual memory address.
7. A machine readable medium capable of storing sequences of instructions, the sequences of instructions including instructions which when executed cause the machine to perform:
associating a guest identifier (ID) with a virtual machine (VM) accessing a virtual memory address;
retrieving a physical memory address by referencing an entry on a table associated with the guest ID; and
intercepting a call to return a size of a region ID and to return a value smaller than a supported size, wherein intercepting the call includes protecting an entry point of a Protection Abstraction Layer.
8. A computer system, comprising:
a bus;
a memory; and
a processor implementing an address translator to retrieve a physical memory address by referencing an entry on a table associated with a guest identifier (ID) associated with a virtual machine accessing the virtual memory address, wherein the processor further implements a region ID size identifier to intercept a call to return a size of a region ID and to return a value smaller than a supported size, wherein intercepting the call includes protecting an entry point of a Protection Abstraction Layer.
9. The computer system of claim 8 , wherein the address translator comprises a region ID identifier to identify a region ID associated with a virtual region number.
10. The computer system of claim 8 , wherein the address translator comprises a guest ID identifier to identify the guest ID associated with the virtual machine.
11. The computer system of claim 8 , wherein the translator comprises a look up unit to identify the physical memory address associated with the guest ID, a region ID, and a virtual page number.
12. The computer system of claim 8 , wherein the processor comprises a virtual machine bit that may be set to indicate whether a region register may be accessed.
13. The computer system of claim 8 , wherein the processor comprises a plurality of region registers to store guest IDs and region IDs associated with virtual memory addresses.
14. The computer system of claim 8 , wherein the processor comprises a translation look-aside buffer (TLB) to store physical addresses corresponding to virtual memory addresses associated with more than one virtual machine.
15. A method for managing virtual memory addresses, comprising:
associating a guest identifier (ID) with a virtual machine (VM) accessing a virtual memory address;
retrieving a physical memory address by referencing an entry on a table associated with the guest ID; and
intercepting a call to return a size of a region ID and to return a value smaller than a supported size, wherein intercepting the call includes providing a substitute Protection Abstraction Layer firmware.
16. The method of claim 15 , wherein retrieving the physical memory address comprises referencing the entry on the table associated with the guest ID, a region ID, and a virtual page number associated with the virtual memory address.
17. The method of claim 15 , wherein the table resides in a translation look-aside buffer (TLB).
18. The method of claim 15 , further comprising determining a region ID assigned to a virtual region corresponding to a virtual region number in the virtual memory address.
19. The method of claim 18 , wherein determining the region ID comprises reading a region register associated with a virtual region corresponding to the virtual region number.
20. The method of claim 15 , further comprising reading the guest ID from a region register associated with a virtual region corresponding to a virtual region number in the virtual memory address.
21. A machine readable medium capable of storing sequences of instructions, the sequences of instructions including instructions which when executed cause the machine to perform:
associating a guest identifier (ID) with a virtual machine (VM) accessing a virtual memory address;
retrieving a physical memory address by referencing an entry on a table associated with the guest ID; and
intercepting a call to return a size of a region ID and to return a value smaller than a supported size, wherein intercepting the call includes providing a substitute Protection Abstraction Layer firmware.
22. A computer system, comprising:
a bus;
a memory; and
a processor implementing an address translator to retrieve a physical memory address by referencing an entry on a table associated with a guest identifier (ID) associated with a virtual machine accessing the virtual memory address, wherein the processor further implements a region ID size identifier to intercept a call to return a size of a region ID and to return a value smaller than a supported size, wherein intercepting the call includes providing a substitute Protection Abstraction Layer firmware.
23. The computer system of claim 22 , wherein the address translator comprises a region ID identifier to identify a region ID associated with a virtual region number.
24. The computer system of claim 22 , wherein the address translator comprises a guest ID identifier to identify the guest ID associated with the virtual machine.
25. The computer system of claim 22 , wherein the translator comprises a look up unit to identify the physical memory address associated with the guest ID, a region ID, and a virtual page number.
26. The computer system of claim 22 , wherein the processor comprises a virtual machine bit that may be set to indicate whether a region register may be accessed.
27. The computer system of claim 22 , wherein the processor comprises a plurality of region registers to store guest IDs and region IDs associated with virtual memory addresses.
28. The computer system of claim 22 , wherein the processor comprises a translation look-aside buffer (TLB) to store physical addresses corresponding to virtual memory addresses associated with more than one virtual machine.