Granted Patent
Utility
US 6,768,297 · App. 09/725,401
High speed VLSI digital tester architecture for real-time output timing acquisition, results accumulation, and analysis
Inventors:
John C. Johnson, Christopher J. Nelson, Donald E. Edenfeld
Patented Case
View Patent ↗
Granted: Jul 27, 2004
Filed: Nov 29, 2000
Inventors
John C. Johnson
Christopher J. Nelson
Donald E. Edenfeld
Assignee (at issue)
Intel Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.