IP Library Granted Patent US 8,175,823
Granted Patent B2
US 8,175,823 · App. 12/316,900 · Granted May 8, 2012

Probing analog signals

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,175,823
App. No.
12/316,900
Granted
May 8, 2012
Kind
B2
Abstract

A device, comprising a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage and an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.

Claims (20)

1. A device, comprising:

a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage, and

an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.

2. The device according to claim 1 , wherein the monitoring slicer is adapted to only operate when the device is in a test mode.

3. The device according to claim 1 , comprising a reference voltage source adapted to provide a plurality of different reference voltage levels to the monitoring slicer.

4. The device according to claim 3 , wherein the reference voltage source is adapted to change the reference voltage level it provides at predetermined intervals.

5. The device according to claim 3 , wherein the reference voltage source is adapted to change the reference voltage level it provides responsive to an analysis of the result of the operative unit.

6. The device according to claim 1 , comprising a controller configured to periodically insert marker bits within the provided sequence of digital outputs in a manner such that the indication marker bits are located at same relative positions within a plurality of repetitions of a test signal provided to the device.

7. The device according to claim 6 , wherein the controller is adapted to insert marker bits which indicate the current reference voltage of the reference voltage source.

8. The device according to claim 6 , wherein the controller is adapted to insert marker bits at times determined responsive to an output of the operative unit.

9. The device according to claim 1 , wherein the sequence of digital outputs from the monitoring slicer includes a single bit for each comparison.

10. The device according to claim 1 , comprising a serial-input parallel-output unit configured to group bits of the sequence of digital outputs into words for retrieval by an external unit.

11. An internal signal determination system, comprising:

a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage from a reference voltage generation unit;

an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer;

a test signal source adapted to provide a test signal to the operative unit;

a data acquisition unit adapted to collect comparison results from the monitoring slicer; and

a processor configured to estimate the internal signal based on comparison results collected by the signal retriever for a plurality of different reference voltage levels.

12. The system according to claim 11 , wherein the reference voltage generation unit is a sub-unit included within a same physical unit including the operative unit.

13. The system according to claim 11 , wherein the reference voltage generation unit is external to the physical unit including the operative unit.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2016
From: INTEL CORPORATION
To: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
Reel/Frame 037733/0440 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2009
From: MEZER, AMIR; BENHAMOU, ASSAF
To: INTEL CORPORATION
Reel/Frame 022831/0357 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2009
From: MEZER, AMIR; BENHAMOU, ASSAF
To: INTEL CORPORATION
Reel/Frame 022710/0258 →