IP Library Granted Patent US 8,401,025
Granted Patent B2
US 8,401,025 · App. 12/768,852 · Granted Mar 19, 2013

Windowing technique for adaptive clock recovery and other signal-processing applications

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,401,025
App. No.
12/768,852
Granted
Mar 19, 2013
Kind
B2
Abstract

In one embodiment, an adaptive clock recovery (ACR) system generates a current delay-offset estimate value (D OE (i)) using a window technique that selects the larger of (i) the maximum delay-offset value (D OP ) in the previous window and (ii) the maximum delay-offset value so far (D OM ) in current window. This windowing technique can be implemented without having to store all of the individual values over a specified window size, as in a conventional sliding window technique. This windowing technique can be used to find extreme (i.e., either maximum or minimum) values for applications other than ACR systems.

Claims (44)

1. A machine-implemented windowing method for finding an extreme value, the method comprising:

(a) determining and storing a previous extreme value for a previous window corresponding to a previous plurality of items; and

(b) for each item in a current window corresponding to a current plurality of items:

(b1) determining and storing a current extreme value so far in the current window corresponding to said each item and any previously processed items in the current window;

(b2) determining and storing an overall extreme value based on the previous extreme value and the current extreme value so far; and

(b3) performing further processing associated with the items based on the overall extreme value, without storing the current plurality of items corresponding to the current window for a subsequent window, wherein, at the end of the current window:

the current window becomes the previous window;

the previous extreme value is updated to be equal to the current extreme value so far; and

the current extreme value so far is re-initialized for a new current window, wherein:

the items are received packets in a packet-based communication system;

the previous extreme value is a maximum delay-offset value for the previous window of received packets;

the current extreme value so far is a maximum delay-offset value so far for the current window of received packets;

the overall extreme value is a current delay-offset estimate value;

the further processing generates, based on the current delay-offset estimate value, an output phase signal that can be used to generate a recovered clock signal; and

the method is implemented by an adaptive clock recovery (ACR) system in a receiver of the packet-based communication system.

2. The method of claim 1 , wherein the ACR system comprises:

a first closed-loop control processor that generates a reference phase signal from an input phase signal representing packet delay values corresponding to arrival times of the packets at the receiver;

a delay-offset estimation component that implements the windowing method, based on the packet delay values and the reference phase signal, to generate the current delay-offset estimate value representative of a delay-floor phase offset for the packet arrival times relative to the reference phase signal;

a delay-offset compensation component that generates a delay-offset-compensated phase signal based on the reference phase signal and the current delay-offset estimate value; and

a second closed-loop control processor that generates, from the delay-offset-compensated phase signal, the output phase signal that can be used to generate the recovered clock signal.

3. An adaptive clock recovery (ACR) system for a receiver, the ACR system comprising:

a first closed-loop control processor that generates a reference phase signal from an input phase signal representing packet delay values corresponding to arrival times of packets at the receiver;

a delay-offset estimation component that implements a windowing method based on the packet delay values and the reference phase signal to generate a delay-offset estimate signal representative of a delay-floor phase offset for the packet arrival times relative to the reference phase signal;

a delay-offset compensation component that generates a delay-offset-compensated phase signal based on the reference phase signal and the delay-offset estimate signal; and

a second closed-loop control processor that generates, from the delay-offset-compensated phase signal, an output phase signal that can be used to generate a recovered clock signal, wherein, to implement the windowing method, the delay-offset estimation component:

(a) determines and stores a previous maximum delay-offset value for a previous window corresponding to a previous plurality of received packets; and

(b) for each received packet in a current window corresponding to a current plurality of received packets:

(b1) determines and stores a current maximum delay-offset value so far in the current window corresponding to said each received packet and any previously received packets in the current window; and

(b2) determines and stores a current delay-offset estimate value based on the previous maximum delay-offset value and the current maximum delay-offset value so far, without storing all of the delay-offset values corresponding to the current window for a subsequent window, wherein, at the end of the current window:

the current window becomes the previous window;

the previous maximum delay-offset value is updated to be equal to the current maximum delay-offset value so far; and

the current maximum delay-offset value so far is re-initialized for a new current window.

4. A receiver-implemented method for recovering a clock signal in a packet system, the method comprising:

(a) generating a reference phase signal from an input phase signal representing packet delay values corresponding to arrival times of packets at the receiver;

(b) implementing a windowing method based on the packet delay values and the reference phase signal to generate a delay-offset estimate signal representative of a delay-floor phase offset for the packet arrival times relative to the reference phase signal;

(c) generating a delay-offset-compensated phase signal based on the reference phase signal and the delay-offset estimate signal; and

(d) generating, from the delay-offset-compensated phase signal, an output phase signal that can be used to generate the recovered clock signal, wherein, the windowing method comprises:

(b1) determining and storing a previous maximum delay-offset value for a previous window corresponding to a previous plurality of received packets; and

(b2) for each received packet in a current window corresponding to a current plurality of received packets:

(b2i) determining and storing a current maximum delay-offset value so far in the current window corresponding to said each received packet and any previously received packets in the current window; and

(b2ii) determining and storing a current delay-offset estimate value based on the previous maximum delay-offset value and the current maximum delay-offset value so far, without storing all of the delay-offset values corresponding to the current window for a subsequent window, wherein, at the end of the current window:

the current window becomes the previous window;

the previous maximum delay-offset value is updated to be equal to the current maximum delay-offset value so far; and

the current maximum delay-offset value so far is re-initialized for a new current window.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2016
From: INTEL CORPORATION
To: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
Reel/Frame 037733/0440 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded May 29, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION
Reel/Frame 035797/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2010
From: BEDROSIAN, P. STEPHAN
To: LSI CORPORATION
Reel/Frame 024299/0545 →