Copying data to a cache using direct memory access
View Patent ↗An apparatus having a first cache and a controller is disclosed. The first cache may be configured to assert a first signal after receiving given information in response to being ready to receive additional information. The controller may be configured to (i) fetch the given information from a memory to the first cache and (ii) prefetch first information in a direct memory access transfer from the memory to the first cache in response to the assertion of the first signal.
1. An apparatus comprising:
a first of a plurality of caches configured to assert a first signal in response to being ready to receive additional information; and
a controller configured to (i) select said first cache in response to a condition of first information stored in a memory and (ii) copy said first information in a direct memory access transfer from said memory to said first cache in response to both said assertion of said first signal and said selection of said first cache; wherein
(i) said memory occupies a memory address range inside a predetermined range, (ii) said first cache occupies a first address range inside said predetermined range and outside said memory address range and (iii) said copy of said first information mirrors one or more first pages of said memory address range into said first address range.
2. The apparatus according to claim 1 , further comprising a second of said caches configured to assert a second signal to said controller.
3. The apparatus according to claim 2 , wherein said controller is further configured to (i) select said second cache in response to a condition of second information stored in said memory and (ii) copy said second information from said memory to said second cache in response to said assertion of said second signal.
4. The apparatus according to claim 1 , wherein (i) a second of said caches occupies a second address range inside said predetermined range and outside both said memory address range and said first address range and (ii) a copy of second information from said memory to said second cache mirrors one or more second pages of said memory address range into said second address range.
5. The apparatus according to claim 1 , wherein said condition comprises an access address of said first information.
6. The apparatus according to claim 1 , wherein said condition comprises an address range of said first information.
7. The apparatus according to claim 1 , wherein said condition comprises one or more bits in said first information.
8. The apparatus according to claim 1 , wherein said controller is further configured to cancel said copy of said first information in response to said first information being absent from a list of active tasks.
9. The apparatus according to claim 1 , wherein said controller is further configured to translate a physical address of said first information as read from said memory into a cache address in said first cache.
10. A method for direct memory access cache copying, comprising the steps of:
(A) asserting a first signal from a first of a plurality of caches to a controller in response to said first cache being ready to receive additional information;
(B) selecting said first cache in response to a condition of first information stored in a memory; and
(C) copying said first information in a direct memory access transfer from said memory to said first cache in response to both said assertion of said first signal and said selecting of said first cache; wherein
(i) said memory occupies a memory address range inside a predetermined range, (ii) said first cache occupies a first address range inside said predetermined range and outside said memory address range and (iii) said copying of said first information mirrors one or more first pages of said memory address range into said first address range.
11. The method according to claim 10 , further comprising the step of:
asserting a second signal from a second of said caches to said controller.
12. The method according to claim 11 , further comprising the steps of:
selecting said second cache in response to a condition of second information stored in said memory; and
copying said second information from said memory to said second cache in response to said assertion of said second signal.
13. The method according to claim 10 , wherein (i) a second of said caches occupies a second address range inside said predetermined range and outside both said memory address range and said first address range and (ii) copying of second information from said memory to said second cache mirrors one or more second pages of said memory address range into said second address range.
14. The method according to claim 10 , wherein said condition comprises an access address of said first information received by said controller.
15. The method according to claim 10 , wherein said condition comprises an address range of said first information.
16. The method according to claim 10 , wherein said condition comprises one or more bits in said first information.
17. The method according to claim 10 , further comprising the step of:
cancelling said copying of said first information in response to said first information being absent from a list of active tasks.
18. An apparatus comprising:
a plurality of caches configured to assert a plurality of signals each in response to being ready to receive additional information; and
a controller configured to (i) select a first of said caches in response to a condition of first information stored in a memory and (ii) copy said first information from said memory to said first cache in response to both said assertion of a corresponding first of said signals and said selection of said first cache, wherein (a) said memory occupies a memory address range inside a predetermined range, (b) said first cache occupies a first address range inside said predetermined range and outside said memory address range and (c) said copy of said first information mirrors one or more first pages of said memory address range into said first address range.