IP Library Granted Patent US 9,612,794
Granted Patent B2
US 9,612,794 · App. 13/661,355 · Granted Apr 4, 2017

Combined RF equalizer and I/Q imbalance correction

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Quick Facts
Patent No.
US 9,612,794
App. No.
13/661,355
Granted
Apr 4, 2017
Kind
B2
Abstract

Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.

Claims (112)

1. An apparatus of a user equipment (UE) comprising:

a digital front end arranged to perform signal processing on signals for transmission from the UE and received at the UE, the digital front end comprising:

a combined system comprising radio frequency (RF) equalizer circuitry and in-phase/quadrature-phase (IQ) imbalance correction (IQIC) stage circuitry in a single stage, the combined system implemented as a first and second complex finite impulse response (FIR) filter disposed in parallel and an adder to sum outputs of the first and second complex FIR filters, the first and second complex FIR filters respectively comprising coefficients c and d, where c is the convolution of a and h, and d is the convolution of b and h, h is an impulse response of the RF equalizer circuitry alone, and a and b are linear combinations of IQ correction coefficients of real and imaginary components of the IQIC stage circuitry alone, and

an output of the combined system is:

y

IQE

,

n

=

f

(

x

)

=

k

=

1

M

c

k

·

x

n

-

k

+

k

=

1

M

d

k

·

x

n

-

k

*

where M is a filter length of the first and second complex FIR filters and x, x* are complex conjugates of an input signal and are respectively supplied to the first and second complex FIR filter.

2. The apparatus of claim 1 , wherein the digital front end further comprises:

a channel filter and digital up conversion (DUC) stage arranged to convert a baseband transmit signal to an intermediate frequency (IF) signal and filter the IF signal to produce a filtered IF signal; and

a crest factor reduction (CFR) stage arranged to limit a peak-to-average ratio of the filtered IF signal.

3. The apparatus of claim 2 , wherein the digital front end further comprises:

a digital pre-distortion (DPD) stage arranged to linearize a signal from the CFR stage and provide an output to the combined system.

4. The apparatus of claim 1 , further comprising:

an antenna configured to transmit the output of the combined system or receive an input signal to be supplied to the digital front end.

5. The apparatus of claim 1 wherein:

the first and second complex FIR filters comprise a plurality of taps at a sampling rate of 307.2 million samples per second (MSPS).

6. The apparatus of claim 5 wherein:

each tap implements f(x) using a plurality of multiply-accumulate (MAC) operations.

7. The apparatus of claim 6 wherein:

four MAC operations are used per tap.

8. The apparatus of claim 5 wherein:

each of the first and second complex FIR filters comprises 32 taps.

9. An apparatus comprising:

a digital front end arranged to perform signal processing on signals transmitted to user equipment (UE) and received from the UE, the digital front end comprising:

a combined system comprising radio frequency (RF) equalizer circuitry and in-phase/quadrature-phase (IQ) imbalance correction (IQIC) stage circuitry in a single stage, the combined system arranged to compensate for dispersion in a transmitter or receiver RF path and for a frequency dependent linear response of a power amplifier along the RF path and RF circuits in a transmitter chain and arranged to compensate for an imbalance between an IQ ratio of an input RF signal, the combined system comprising a plurality of parallel finite impulse response (FIR) filters whose outputs are combined to provide a combined output, the first and second FIR filters respectively comprising coefficients that are different convolutions of an impulse response of the RF equalizer circuitry alone and linear combinations of IQ correction coefficients of real and imaginary components of the IQIC stage circuitry alone, and

the combined output is:

y

IQE

,

n

=

f

(

x

)

=

k

=

1

M

c

k

·

x

n

-

k

+

k

=

1

M

d

k

·

x

n

-

k

*

where M is a filter length of the first and second complex FIR filters and x, x* are complex conjugates of the input RF signal and are respectively supplied to the first and second complex FIR filter, and c and d are respectively the first and second FIR filter components.

10. The apparatus of claim 9 , wherein the digital front end further comprises:

a channel filter and digital up conversion (DUC) stage arranged to upconvert a baseband transmit signal and filter the upconverted signal to produce a filtered signal; and

a crest factor reduction (CFR) stage arranged to limit a peak-to-average ratio of the filtered signal.

11. The apparatus of claim 10 , wherein the digital front end further comprises:

a digital pre-distortion (DPD) stage arranged to linearize a signal from the CFR stage and provide an output to the combined system.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded May 29, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION
Reel/Frame 035797/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2013
From: AZADET, KAMERAN; OTHMER, JOSEPH H.; YU, MENG-LIN
To: LSI CORPORATION
Reel/Frame 029640/0010 →