Digital signal processor having instruction set with a logarithm function using reduced look-up table
View Patent ↗A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function for an input value, x, by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following the most significant bit, wherein the number is small relative to a number of bits in the input value, x; obtaining a value Log 2 ( 1 + 1 2 q ) from a first look-up table based on the second part, q; computing an epsilon term, ε, using the expression 2 - N 1 + 1 2 q r ; evaluating an expression Log 2 (1+ε) using a polynomial approximation, such as a cubic approximation; and determining the logarithm function for the input value, x, by summing the values of N, Log Z ( 1 + 1 2 q ) and Log 2 (1+ε).
1. A method performed by a vector-based digital signal processor for evaluating a non-linear logarithm function for an input vector, x, said method comprising:
obtaining one or more logarithm software instructions that implement said non-linear logarithm function;
in response to at least one of said obtained logarithm software instructions, invoking at least one hardware functional unit that implements said one or more logarithm software instructions to perform the following steps in hardware for each component of said input vector, x, to produce a corresponding component of an output vector, wherein said input vector, x, comprises a plurality of said components and wherein said vector-based digital signal processor processes said plurality of components substantially simultaneously:
decomposing each component of said input vector, x, to a first part, N, a second part, q, and a remaining part, r, wherein said first part, N, is identified by a position of a most significant bit of said input vector, x, and said second part, q, is comprised of a number of bits following said most significant bit, wherein said number is small relative to a number of bits in said input vector, x;
obtaining a value
Log
2
(
1
+
1
2
q
)
from a first look-up table in a random access memory (RAM) of said vector-based digital signal processor based on said second part, q;
computing an epsilon term, E, using the expression
2
-
N
1
+
1
2
q
r
;
evaluating an expression Log: (1+ε) using a polynomial approximation; and
determining said logarithm function for said input vector, x, by summing said values of N,
Log
Z
(
1
+
1
2
q
)
and Log 2 (1+ε) to produce said corresponding component of said output vector, wherein a predefined software instruction keyword for said non-linear logarithm function is part of an instruction set of said vector-based digital signal processor.
2. The method of claim 1 , further comprising the step of translating an initial basis of said logarithm function from a binary representation to an arbitrary basis, Y, by multiplying a result of said determining step by Log Y (2), where log Y (2), is obtained from a look-up table.
3. The method of claim 1 , further comprising the step of obtaining a value
(
1
+
1
2
q
)
-
1
from a second look-up table.
4. The method of claim 1 , wherein said step of computing said epsilon term, ε, further comprises the steps of shifting r by N and multiplying by
(
1
+
1
2
q
)
-
1
.
5. The method of claim 1 , wherein said polynomial approximation is a cubic approximation.
6. The method of claim 1 , wherein entries in said look-up table have a fewer number of bits than a number of bits in said input vector, x.
7. A vector-based digital signal processor for evaluating a non-linear logarithm function for an input vector, x, comprising:
an input for receiving one or more logarithm software instructions that implement said non-linear logarithm function;
a memory storing at least one look-up table; and
at least one processor, coupled to the memory, operative to:
in response to at least one of said obtained logarithm software instructions, invoke at least one hardware functional unit that implements said one or more non-linear logarithm software instructions to perform the following steps in hardware for each component of said input vector, x, to produce a corresponding component of an output vector, wherein said input vector, x, comprises a plurality of said components and wherein said vector-based digital signal processor processes said plurality of components substantially simultaneously:
decompose each component of said input vector, x, to a first part, N, a second part, q, and a remaining part, r, wherein said first part, N, is identified by a position of a most significant bit of said input vector, x, and said second part, q, is comprised of a number of bits following said most significant bit, wherein said number is small relative to a number of bits in said input vector, x;
obtain a value
Log
2
(
1
+
1
2
q
)
from a first look-up table in a random access memory (RAM) of said vector-based digital signal processor based on said second part, q;
compute an epsilon term, C, using the expression
2
-
N
1
+
1
2
q
r
;
evaluate an expression Log 2 (1+ε) using a polynomial approximation; and
determine said logarithm function for said input vector, x, by summing said values of N,
Log
Z
(
1
+
1
2
q
)
and Log 2 (1+ε) to produce said corresponding component of said output vector, wherein a predefined software instruction keyword for said non-linear logarithm function is part of an instruction set of said vector-based digital signal processor.
8. The digital signal processor of claim 7 , wherein said processor is further configured to translate an initial basis of said input value, x, to an arbitrary basis, Y, by multiplying a result of said logarithm function by Log Y (2), where log Y (2), is obtained from a look-up table.
9. The digital signal processor of claim 7 , wherein said processor is further configured to obtain a value
(
1
+
1
2
q
)
-
1
from a look-up table.
10. The digital signal processor of claim 7 , wherein said epsilon term, ε, is computed by shifting r by N and multiplying by
(
1
+
1
2
q
)
-
1
.
11. The digital signal processor of claim 7 , wherein said polynomial approximation is a cubic approximation.
12. The digital signal processor of claim 7 , wherein said digital signal processor executes software instructions from program code.
13. The digital signal processor of claim 7 , wherein entries in said look-up table have a fewer number of bits than a number of bits in said input vector, x.
14. An integrated circuit, comprising:
a digital signal processor for evaluating a non-linear logarithm function for an input value, x, comprising:
an input for receiving one or more logarithm software instructions that implement said non-linear logarithm function;
a memory storing at least one look-up table; and
at least one processor, coupled to the memory, operative to:
in response to at least one of said obtained logarithm software instructions, invoke at least one hardware functional unit that implements said one or more atomic logarithm software instructions to perform the following steps in hardware for each component of said input vector, x, to produce a corresponding component of an output vector, wherein said input vector, x, comprises a plurality of said components and wherein said vector-based digital signal processor processes said plurality of components substantially simultaneously:
decompose each component of said input vector, x, to a first part, N, a second part, q, and a remaining part, r, wherein said first part, N, is identified by a position of a most significant bit of said input vector, x, and said second part, q, is comprised of a number of bits following said most significant bit, wherein said number is small relative to a number of bits in said input vector, x;
obtain a value
Log
2
(
1
+
1
2
q
)
from a first look-up table in a random access memory (RAM) of said vector-based digital signal processor based on said second part, q;
compute an epsilon term, Σ, using the expression
2
-
N
1
+
1
2
q
r
;
evaluate an expression Log 2 (1+ε) using a polynomial approximation; and
determine said logarithm function for said input vector, x, by summing said values of N,
Log
Z
(
1
+
1
2
q
)
and Log 2 (1+Σ) to produce said corresponding component of said output vector, wherein predefined software instruction keyword for said non-linear logarithm function is part of an instruction set of said vector-based digital signal processor.
15. The integrated circuit of claim 14 , wherein said processor is further configured to translate an initial basis of said input value, x, to an arbitrary basis, Y, by multiplying a result of said logarithm function by Log Y (2), where log Y (2), is obtained from a look-up table.
16. The integrated circuit of claim 14 , wherein said processor is further configured to obtain a value
(
1
+
1
2
q
)
-
1
from a look-up table.
17. The integrated circuit of claim 14 , wherein said epsilon term, ε, is computed by shifting r by N and multiplying by
(
1
+
1
2
q
)
-
1
.
18. The integrated circuit of claim 14 , wherein entries in said look-up table have a fewer number of bits than a number of bits in said input vector, x.
19. A method performed by a vector-based digital signal processor for evaluating a logarithm function for an input vector, x, having an initial basis, Z, said method comprising:
obtaining one or more logarithm software instructions that implement said logarithm function;
in response to at least one of said obtained logarithm software instructions, invoking at least one hardware functional unit that implements said one or more logarithm software instructions to perform the following steps in hardware for each component of said input vector, x, to produce a corresponding component of an output vector, wherein said input vector, x, comprises a plurality of said components and wherein said vector-based digital signal processor processes said plurality of components substantially simultaneously:
decomposing each component of said input vector, x, to a first part, N, a second part, q, and a remaining part, r, wherein said first part, N, is identified by a position of a most significant bit of said input vector, x, and said second part, q, is comprised of a number of bits following said most significant bit, wherein said number is small relative to a number of bits in said input vector, x;
obtaining a value
Log
Z
(
1
+
1
Z
q
)
from a first look-up table in a random access memory (RAM) of said vector-based digital signal processor based on said second part, q;
computing an epsilon term, E, using the expression
Z
-
N
1
+
1
Z
q
r
;
evaluating an expression Log z (1+ε) using a polynomial approximation; and
determining said logarithm function for said input vector, x, by summing said values of N,
Log
Z
(
1
+
1
Z
q
)
and Log z (1+ε) to produce said corresponding component of said output vector, wherein a predefined software instruction keyword for said non-linear logarithm function is part of an instruction set of said vector-based digital signal processor.
20. The method of claim 19 , further comprising the step of translating an initial basis of said logarithm function from a binary representation to an arbitrary basis, Y, by multiplying a result of said determining step by Log Y (2), where log Y (2), is obtained from a look-up table.