Maximum likelihood bit-stream generation and detection using M-algorithm and infinite impulse response filtering
View Patent ↗Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.
1. A method, comprising:
applying an M-Algorithm to a target input signal X to perform Maximum Likelihood Sequence Estimation to produce a digital bit stream B, such that after filtering by an Infinite Impulse Response (IIR) filter, the produced digital stream Y produces an error signal with respect to said target input signal X satisfying one or more predefined requirements.
2. The method of claim 1 , wherein said target input signal X comprises a desired transmit signal and said produced digital stream Y comprises an estimate of said desired transmit signal.
3. The method of claim 1 , wherein said one or more predefined requirements comprise a substantially minimum error.
4. The method of claim 3 , wherein said substantially minimum error comprises a difference between a digital output of said IIR filter and said target input signal.
5. The method of claim 1 , wherein said produced digital stream is one of NRZ, BPSK, QPSK, QAM modulation formats.
6. The method of claim 1 , further comprising the step of applying said produced digital stream to one or more of a switching type power amplifier and an analog restitution filter.
7. The method of claim 6 , wherein an output of said analog restitution filter comprises an analog RF signal that approximates said target input signal.
8. The method of claim 6 , wherein said IIR filter has a frequency response that is similar to said analog restitution filter.
9. The method of claim 6 , wherein said analog restitution filter comprises one or more of a passive filter, a resistive-inductive-capacitive (R-L-C) circuit and a transmission line.
10. The method of claim 1 , wherein said IIR filter comprises a passband filter and said target input signal is a baseband signal modulated to an RF frequency in a digital domain.
11. The method of claim 1 , wherein said IIR filter comprises a baseband filter and said target input signal is a baseband signal.
12. The method of claim 1 , wherein said maximum likelihood sequence estimation incorporates and compensates for one or more of a non-linear memory of an RF power amplifier and a digital driver analog circuit.
13. The method of claim 1 , further comprising the step of converting said produced digital stream to an analog signal using a transmitter of a serializer-deserializer device.
14. The method of claim 13 , wherein said method and said serializer-deserializer device are embodied on a System on a Chip.
15. The method of claim 2 , wherein said IIR filter is a model of a transmitter analog output channel that will carry the produced digital stream.
16. The method of claim 1 , wherein said target input signal X comprises an observed analog signal and said produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream.
17. The method of claim 16 , wherein said IIR filter is a model of an analog receive channel that said observed analog signal passed through.
18. The method of claim 16 , wherein said bit detection is employed in one or more of a storage device read channel and a data channel.
19. The method of claim 18 , wherein said maximum likelihood sequence estimation incorporates and compensates for a non-linear memory of one or more of said storage device read channel, said data channel and an analog receive channel.
20. An apparatus, comprising:
an M-Algorithm stage for processing a target input signal X to perform Maximum Likelihood Sequence Estimation to produce a digital bit stream B; and
an Infinite Impulse Response (IIR) filter, such that after filtering by said IIR filter, the produced digital stream Y produces an error signal with respect to said target input signal X satisfying one or more predefined requirements.
21. The apparatus of claim 20 , wherein said target input signal X comprises a desired transmit signal and said produced digital stream Y comprises an estimate of said desired transmit signal.
22. The apparatus of claim 20 , wherein said one or more predefined requirements comprise a substantially minimum error.
23. The apparatus of claim 21 , wherein said IIR filter is a model of a transmitter analog output channel that will carry the produced digital stream.
24. The apparatus of claim 20 , wherein said target input signal X comprises an observed analog signal and said produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream.
25. The apparatus of claim 24 , wherein said IIR filter is a model of an analog receive channel that said observed analog signal passed through.
26. The apparatus of claim 24 , wherein said bit detection is employed in one or more of a storage device read channel and a data channel.
27. An apparatus, comprising:
a memory; and
at least one hardware device, coupled to the memory, operative to:
apply an M-Algorithm to a target input signal X to perform Maximum Likelihood Sequence Estimation to produce a digital bit stream B, such that after filtering by an Infinite Impulse Response (IIR) filter, the produced digital stream Y produces an error signal with respect to said target input signal X satisfying one or more predefined requirements.
28. The apparatus of claim 27 , wherein said target input signal X comprises a desired transmit signal and said produced digital stream Y comprises an estimate of said desired transmit signal.
29. The apparatus of claim 27 , wherein said one or more predefined requirements comprise a substantially minimum error.
30. The apparatus of claim 28 , wherein said IIR filter is a model of a transmitter analog output channel that will carry the produced digital stream.
31. The apparatus of claim 27 , wherein said target input signal X comprises an observed analog signal and said produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream.
32. The apparatus of claim 31 , wherein said IIR filter is a model of an analog receive channel that said observed analog signal passed through.
33. The apparatus of claim 31 , wherein said bit detection is employed in one or more of a storage device read channel and a data channel.