IP Library Granted Patent US 8,381,080
Granted Patent B2
US 8,381,080 · App. 12/815,514 · Granted Feb 19, 2013

Reducing a degree of a polynomial in a polynomial division calculation

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Quick Facts
Patent No.
US 8,381,080
App. No.
12/815,514
Granted
Feb 19, 2013
Kind
B2
Abstract

An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial.

Claims (31)

1. An apparatus comprising:

a lookup table configured to store a plurality of results comprising remainders of divisions by a particular polynomial; and

a circuit configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from said lookup table by indexing said lookup table with each of said data blocks, (iii) generate an intermediate result by concatenating said results fetched from said lookup table and (iv) generate a second polynomial by adding said intermediate result to said end block, wherein said second polynomial has a second degree that is lower than a first degree of said first polynomial.

2. The apparatus according to claim 1 , wherein said circuit is further configured to calculate a final remainder by dividing said second polynomial by said particular polynomial.

3. The apparatus according to claim 2 , wherein said final remainder comprises a cyclic redundancy check of said first polynomial.

4. The apparatus according to claim 1 , wherein said circuit is further configured to (i) substitute said second polynomial as said first polynomial and (ii) repeat said parse of said first polynomial, said fetches of said results, said concatenation of said results and said generation of said second polynomial until said second degree is less than a predetermined degree.

5. The apparatus according to claim 1 , wherein (i) said circuit comprises a pipeline configured to perform said fetches, (ii) said pipeline has a plurality of stages and (iii) each of said fetches is performed by a corresponding one of said stages.

6. The apparatus according to claim 5 , wherein said stages that perform said fetches comprise adjoining stages.

7. The apparatus according to claim 5 , wherein a first number of said stages perform said fetches, (ii) each of said results has a second number of bits and (iii) a difference between said first degree and said second degree matches a product of said first number and said second number.

8. The apparatus according to claim 1 , wherein said fetching of said results are completed before said generation of said second polynomial begins.

9. The apparatus according to claim 1 , wherein all of said fetches are to a single lookup table.

10. The apparatus according to claim 1 , wherein a second remainder produced by dividing said second polynomial by said particular polynomial matches a first remainder produced by dividing said first polynomial by said particular polynomial.

11. A method for reducing a first degree of a first polynomial in a polynomial division calculation, comprising the steps of:

(A) parsing said first polynomial into a plurality of data blocks and an end block;

(B) fetching a plurality of results from a lookup table by indexing said lookup table with each of said data blocks, wherein said results comprise remainders of divisions by a particular polynomial;

(C) generating an intermediate result by concatenating said results fetched from said lookup table; and

(D) generating with a circuit a second polynomial by adding said intermediate result to said end block, wherein said second polynomial has a second degree that is lower than said first degree of said first polynomial.

12. The method according to claim 11 , further comprising the step of:

calculating a final remainder by dividing said second polynomial by said particular polynomial.

13. The method according to claim 12 , wherein said final remainder comprises a cyclic redundancy check of said first polynomial.

14. The method according to claim 11 , further comprising the steps of:

substituting said second polynomial as said first polynomial; and

repeating steps (A) to (D) until said second degree is less than a predetermined degree.

15. The method according to claim 11 , wherein (i) said fetching is performed by a pipeline of said circuit, (ii) said pipeline has a plurality of stages and (iii) each of said fetches is performed by a corresponding one of said stages.

16. The method according to claim 15 , wherein said stages that perform said fetching comprise adjoining stages.

17. The method according to claim 15 , wherein a first number of said stages perform said fetches, (ii) each of said results has a second number of bits and (iii) a difference between said first degree and said second degree matches a product of said first number and said second number.

18. The method according to claim 11 , wherein said fetching of said results are completed before said generating of said second polynomial begins.

19. The method according to claim 11 , wherein a second remainder produced by dividing said second polynomial by said particular polynomial matches a first remainder produced by dividing said first polynomial by said particular polynomial.

20. An apparatus comprising:

means for storing a plurality of results in a lookup table, wherein said results comprise remainders of divisions by a particular polynomial; and

means for processing configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from said lookup table by indexing said lookup table with each of said data blocks, (iii) generate an intermediate result by concatenating said results fetched from said lookup table and (iv) generate a second polynomial by adding said intermediate result to said end block, wherein said second polynomial has a second degree that is lower than a first degree of said first polynomial.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded May 29, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION
Reel/Frame 035797/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: RABINOVITCH, ALEXANDER; KALFON, SHAI
To: LSI CORPORATION
Reel/Frame 024535/0470 →