CONTROLLING A SEQUENCE OF PARALLEL EXECUTIONS
An apparatus having a first circuit and a plurality of second circuits is disclosed. The first circuit may be configured to dispatch a plurality of sets in a sequence. Each set generally includes a plurality of instructions. The second circuits may be configured to (i) execute the sets during a plurality of execution cycles respectively and (ii) stop the execution in a particular one of the second circuits during one or more of the execution cycles in response to an expiration of a particular counter that corresponds to the particular second circuit.
1 . An apparatus comprising:
a first circuit configured to dispatch a plurality of sets in a sequence, wherein each of said sets comprises a plurality of instructions; and
a plurality of second circuits configured to (i) execute said sets during a plurality of execution cycles respectively and (ii) stop said execution in a particular one of said second circuits during one or more of said execution cycles in response to an expiration of a particular counter that corresponds to said particular second circuit.
2 . The apparatus according to claim 1 , wherein (i) said particular counter is programmed with a value, (ii) said sets perform one of a plurality of operations in a program and (iii) said value is smaller than a number of said sets.
3 . The apparatus according to claim 2 , wherein said value is calculated by said program.
4 . The apparatus according to claim 1 , wherein said particular second circuit is further configured to execute a no-operation instruction during said execution cycles after said expiration of said particular counter.
5 . The apparatus according to claim 1 , wherein said particular second circuit is further configured to execute a plurality of particular ones of said instructions in a loop while said particular counter is active.
6 . The apparatus according to claim 5 , wherein said particular second circuit is further configured to store said particular instructions in a particular one of a plurality of buffers, wherein said buffers correspond to said second circuits respectively.
7 . The apparatus according to claim 6 , wherein said particular second circuit is further configured to read said particular instructions in a sequence from said particular buffer in accordance with said loop.
8 . The apparatus according to claim 1 , wherein another of second circuits is further configured to stop said execution of said sets during one or more of said execution cycles in response to an expiration of another counter that corresponds to said another second circuit.
9 . The apparatus according to claim 8 , wherein said particular counter is programmed with a different value than said another counter.
10 . The apparatus according to claim 1 , wherein said apparatus is implemented as one or more integrated circuits.
11 . A method for controlling a sequence of parallel executions, comprising the steps of:
(A) dispatching a plurality of sets in a sequence, wherein each of said sets comprises a plurality of instructions;
(B) executing said sets during a plurality of execution cycles respectively in a plurality of circuits; and
(C) stopping said executing in a particular one of said circuits during one or more of said execution cycles in response to an expiration of a particular counter that corresponds to said particular circuit.
12 . The method according to claim 11 , further comprising the step of:
programming said particular counter with a value, wherein (i) said sets perform one of a plurality of operations in a program and (ii) said value is smaller than a number of said sets.
13 . The method according to claim 12 , wherein said value is calculated by said program.
14 . The method according to claim 11 , further comprising the step of:
executing a no-operation instruction in said particular circuit during said execution cycles after said expiration of said particular counter.
15 . The method according to claim 11 , wherein said particular circuit executes a plurality of particular ones of said instructions in a loop while said particular counter is active.
16 . The method according to claim 15 , further comprising the step of:
storing said particular instructions in a particular one of a plurality of buffers, wherein said buffers correspond to said circuits respectively.
17 . The method according to claim 16 , further comprising the step of:
reading said particular instructions in a sequence from said particular buffer in accordance with said loop.
18 . The method according to claim 11 , further comprising the step of:
stopping said executing of said sets in another of said circuits during one or more of said execution cycles in response to an expiration of another counter that corresponds to said another circuit.
19 . The method according to claim 18 , wherein said particular counter is programmed with a different value than said another counter.
20 . An apparatus comprising:
means for dispatching a plurality of sets in a sequence, wherein each of said sets comprises a plurality of instructions;
means for executing said sets during a plurality of execution cycles respectively; and
means for stopping said executing in a particular one of said means for executing during one or more of said execution cycles in response to an expiration of a particular counter that corresponds to said particular means for executing.