Low depth programmable priority encoders
View Patent ↗An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
1. An apparatus comprising:
a plurality of function circuits configured to generate a plurality of enable signals in response to (i) a request signal and (ii) a priority signal; and
a plurality of logic circuits configured to generate collectively an output signal in response to (i) said enable signals and (ii) said request signal, wherein (a) a combination of said function circuits and said logic circuits establishes a programmable priority encoder and (b) at least three of said enable signals are generated independently of each other.
2. The apparatus according to claim 1 , wherein (i) said request signal has N bits and (ii) a depth through said function circuits and said logic circuits is at most approximately 2 log 2 N levels of two-input Boolean logic gates.
3. The apparatus according to claim 1 , wherein (i) said function circuits comprise a plurality of first circuits and a plurality of second circuits and (ii) a subset of said second circuits receive a corresponding subset of said enable signals.
4. The apparatus according to claim 1 , wherein at least three of said enable signals are routed exclusively to said logic circuits.
5. The apparatus according to claim 1 , wherein said function circuits comprise a plurality of first circuits interconnected in a pattern forming a plurality of columns and a plurality of rows.
6. The apparatus according to claim 5 , wherein each of said rows has a different number of said first circuits.
7. The apparatus according to claim 5 , wherein each of said rows has a common number of said first circuits.
8. The apparatus according to claim 1 , further comprising a plurality of first circuits coupled to said function circuits and configured to invert a respective bit of said request signal.
9. The apparatus according to claim 1 , wherein each of said function circuits comprises a plurality of Boolean logic gates configured to generate (i) a first signal=A OR (B AND C) and (ii) a second signal=B AND D, where A, B, C and D are inputs.
10. The apparatus according to claim 1 , wherein each of said function circuits comprises a plurality of Boolean logic gates configured to generate one of said enable signals=A OR (B AND C), where A, B and C are inputs.
11. The apparatus according to claim 1 , wherein each of said logic circuits comprises a Boolean AND logic gate.
12. The apparatus according to claim 1 , wherein said programmable priority encoder is configured to (i) divide said request signal into one or more subsets, one of said subsets corresponding to each given bit of said priority signal having a predetermined logical value and (ii) pass a highest priority bit in each respective one of said subsets from said request signal to said output signal.
13. The apparatus according to claim 1 , wherein said programmable priority encoder comprises a circular programmable priority encoder in which an initial state of said enable signals matches a final state of said enable signals.
14. The apparatus according to claim 1 , wherein (i) said request signal has 26 bits and (ii) a depth through said function circuits and said logic circuits is at most nine levels of two-input Boolean logic gates.
15. A method of priority encoding, comprising the steps of:
(A) generating a plurality of enable signals in response to (i) a request signal and (i) a priority signal using a plurality of function circuits; and
(B) generating an output signal in response to (i) said enable signals and (ii) said request signal using a plurality of logic circuits collectively, such wherein (a) a combination of said function circuits and said logic circuits establishes a programmable priority encoder and (b) at least three of said enable signals are generated independently of each other.
16. The method according to claim 15 , wherein (i) said request signal has N bits and (ii) a depth through said function circuits and said logic circuits is at most approximately 2 log 2 N levels of two-input Boolean logic gates.
17. The method according to claim 15 , wherein said functions circuits comprise a plurality of first circuits and a plurality of second circuits, the method further comprising the step of:
routing a subset of said enable signals to a corresponding subset of said second circuits.
18. The method according to claim 15 , further comprising the step of:
routing at least three of said enable signals exclusively to said logic circuits.
19. The method according to claim 15 , further comprising the step of:
routing a plurality of bits of said request signal to each of said function circuits.
20. An apparatus comprising:
means for generating a plurality of enable signals in response to (i) a request signal and (ii) a priority signal; and
means for generating an output signal in response to (i) said enable signals and (ii) said request signal, wherein (a) a combination of said means for generating said enable signals and said means for generating said output signal establishes a programmable priority encoder and (b) at least three of said enable signals are generated independently of each other.