Vector processor having instruction set with vector convolution function for fir filtering

1. A method performed by a vector processor for performing an instruction to perform a convolution between an input signal and a filter impulse response, said method comprising:

obtaining a vector comprised of at least N 1 +N 2 - 1 input samples;

obtaining N 2 time shifted versions of said vector, wherein each time shifted version comprises N 1 samples; and

performing a weighted sum of said time shifted versions of said vector by a vector of N 1 coefficients; and

producing an output vector comprising one output value for each of said weighted sums, wherein said filter impulse response is expressed using a plurality of coefficients and wherein a number of coefficients supported by said convolution is less than a number of coefficients in a filter; wherein said method further comprises the step of iteratively processing smaller chunks of a larger filter; wherein an output of each iteration is accumulated for each chunk until all of said larger filter is processed.

2. The method of claim 1 , wherein said N 2 time shifted versions of said vector includes a zero shifted version of said vector.

3. The method of claim 1 , wherein said method is performed by a vector processor in response to one or more vector convolution software instructions having a vector comprised of said N 1 +N 2 - 1 input samples.

4. The method of claim 1 , wherein said vector processor executes software instructions from program code.

5. The method of claim 1 , wherein said vector comprises a plurality of real or complex input samples and said filter impulse response is expressed using a plurality of coefficients that are real or complex.

6. The method of claim 1 , wherein said filter impulse response is expressed using a plurality of coefficients and wherein said coefficients are processed with a reduced number of bits using a plurality of iterations until all bits of said coefficients are processed; wherein an output of each iteration is shifted and accumulated until all bits of said coefficients are processed.

7. A vector processor that performs a convolution between an input signal and a filter impulse response, comprising:

a memory; and

at least one hardware device, coupled to the memory, operative to execute a single decoded instruction stored in memory to:

obtain a vector comprised of at least N 1 +N 2 - 1 input samples;

obtain N 2 time shifted versions of said vector, wherein each time shifted version comprises N 1 samples; and

perform a weighted sum of said time shifted versions of said vector by a vector of N 1 coefficients; and

produce an output vector comprising one output value for each of said weighted sums, wherein said filter impulse response is expressed using a plurality of coefficients and wherein a number of coefficients supported by said convolution is less than a number of coefficients in a filter; wherein smaller chunks of a larger filter are iteratively processed and an output of each iteration is accumulated for each chunk until all of said larger filter is processed.

8. The vector processor of claim 7 , wherein vector processor performs said convolution in response to one convolution software instruction having a vector comprised of said N 1 +N 2 - 1 input samples.

9. The vector processor of claim 7 , wherein said vector processor executes software instructions from program code.

10. The vector processor of claim 7 , wherein said vector comprises a plurality of real or complex input samples and said filter impulse response is expressed using a plurality of coefficients that are real or complex.

11. The vector processor of claim 7 , wherein said filter impulse response is expressed using a plurality of coefficients and wherein said coefficients are processed with a reduced number of bits using a plurality of iterations until all bits of said coefficients are processed; wherein an output of each iteration is shifted and accumulated until all bits of said coefficients are processed.