Cache prefetch learning

1. An apparatus comprising:

a processor configured to generate (i) a plurality of access addresses and (ii) a plurality of program counter values corresponding to said access addresses, wherein said processor is implemented with hardware;

a cache configured to present in response to said access addresses (i) a plurality of data words, (ii) a plurality of address information corresponding to said data words and (iii) a hit/miss signal; and

a circuit configured to (a) record a plurality of events in a file in response to a plurality of cache misses while in a first mode and (b) initiate a prefetch of a first of said data words in response to reaching a particular one of said program counter values while in a second mode, wherein (A) a first of said events in said file due to a first of said cache misses comprises (i) a first of said program counter values, (ii) a first of said address information and (iii) a first time to transfer said first data word from a memory to said cache, (B) one of said cache or said circuit measures said first time to transfer said first data word from said memory to said cache, (C) said address information identifies where said data words missed in said cache are located in said memory, and (D) said particular program counter value is reached at least said first time before said first program counter value such that said prefetch of said first data word is complete before said first program counter value is reached.

2. The apparatus according to claim 1 , wherein (i) said cache is further configured to assert said hit/miss signal in a miss state in response to said cache misses and (ii) said circuit records said first event in response to said assertion of said hit/miss signal corresponding to said first program counter value.

3. The apparatus according to claim 1 , wherein (i) said cache is further configured to delay presentation of said data words in response to said cache misses and (ii) said circuit records said first event in response to observing said delay of said first data word from said cache.

4. The apparatus according to claim 1 , further comprising a bus configured to transfer said data words from said memory to said cache, wherein said circuit records said first event in response to monitoring said transfer of said first data word on said bus.

5. The apparatus according to claim 1 , wherein said file is accessible from outside of said circuit.

6. The apparatus according to claim 1 , wherein said circuit is configured to receive said file from a source outside of said circuit.

7. The apparatus according to claim 6 , wherein (i) said file as received from said source includes a second of said events and (ii) said circuit is further configured to initiate a prefetch of a second of said data words based on said second event.

8. The apparatus according to claim 1 , wherein said first event includes a number of times said first program counter value causes said cache misses.

9. The apparatus according to claim 1 , wherein said apparatus is implemented as an integrated circuit.

10. A method of prefetch learning for a cache, comprising the steps of:

(A) generating (i) a plurality of access addresses and (ii) a plurality of program counter values corresponding to said access addresses;

(B) presenting from said cache in response to said access addresses (i) a plurality of data words, (ii) a plurality of address information corresponding to said data words and (iii) a hit/miss signal;

(C) measuring a first time to transfer a first of said data words from a memory to said cache;

(D) recording a plurality of events in a file in response to a plurality of cache misses while in a first mode; and

(E) initiating a prefetch of said first data word in response to reaching a particular one of said program counter values while in a second mode, wherein (a) a first of said events in said file due to a first of said cache misses comprises (i) a first of said program counter values, (ii) a first of said address information, (iii) said first time to transfer said first data word from said memory to said cache and (b) said address information identifies where said data words missed in said cache are located in said memory and (c) said particular program counter value is reached at least said first time before said first program counter value such that said prefetch of said first data word is complete before said first program counter value is reached.

11. The method according to claim 10 , further comprising the step of:

asserting said hit/miss signal in a miss state in response to said cache misses, wherein said first event is recorded in response to said assertion of said hit/miss signal corresponding to said first program counter value.

12. The method according to claim 10 , further comprising the step of:

delaying presentation of said data words from said cache in response to said cache misses, wherein said first event is recorded in response to observing said delaying of said first data word from said cache.

13. The method according to claim 10 , further comprising the step of:

transferring said data words on a bus from said memory to said cache, wherein said first event is recorded in response to monitoring said transfer of said first data word on said bus.

14. The method according to claim 10 , wherein (i) said file is stored in a circuit and (ii) said file is accessible from outside of said circuit.

15. The method according to claim 10 , wherein (i) said file is stored in a circuit and (ii) said file is received from a source outside of said circuit.

16. The method according to claim 15 , wherein said file as received from said source includes a second of said events, the method further comprising the step of:

initiating a prefetch of a second of said data words based on said second event.

17. The method according to claim 10 , wherein said first event includes a number of times said first program counter value causes said cache misses.

18. The method according to claim 10 , wherein (i) said measuring of said first time is performed internal to said cache in response to a corresponding one of said cache misses and (ii) said first time is presented from said cache in a signal.

19. The method according to claim 10 , wherein said measuring of said first time monitors an amount of time that said program counter values remain unchanged after a corresponding one of said cache misses.

20. An apparatus comprising:

means for processing configured to generate (i) a plurality of access addresses and (ii) a plurality of program counter values corresponding to said access addresses;

means for caching configured to present in response to said access addresses (i) a plurality of data words, (ii) a plurality of address information corresponding to said data words and (iii) a hit/miss signal;

means for measuring a first time to transfer a first of said data words from a memory to said means for caching; and

means for learning configured to record a plurality of events in a file in response to a plurality of cache misses while in a first mode; and

means for initiating a prefetch of said first data word in response to reaching a particular one of said program counter values while in a second mode, wherein (A) a first of said events in said file due to a first of said cache misses comprises (i) a first of said program counter values, (ii) a first of said address information and (iii) said first time to transfer said first data word from said memory to said means for caching, (B) said address information identifies where said data words missed in said cache are located in said memory and (C) said particular program counter value is reached at least said first time before said first program counter value such that said prefetch of said first data word is complete before said first program counter value is reached.