COMPILED CONTROL CODE PARALLELIZATION BY HARDWARE TREATMENT OF DATA DEPENDENCY
An apparatus comprising a buffer and a processor. The buffer may be configured to store a plurality of fetch sets. The processor may be configured to perform a change of flow operation based upon at least one of (i) a comparison between addresses of two memory locations involved in each of two memory accessess, (ii) a first predefined prefix code, and (iii) a second predefined prefix code.
1 . An apparatus comprising:
a buffer configured to store a plurality of fetch sets; and
a processor configured to perform a change of flow operation based upon at least one of (i) a comparison between addresses of two memory locations involved in each of two memory accesses, (ii) a first predefined prefix code, and (iii) a second predefined prefix code.
2 . The apparatus according to claim 1 , wherein at least one of said fetch sets comprises a prefix word and said processor is configured to select either a dual path fetch operation or a dual path fetch and execute operation in response to said prefix word containing said first predefined prefix code or said second predefined prefix code, respectively.
3 . The apparatus according to claim 1 , wherein each of said fetch sets comprises a variable length execution set.
4 . The apparatus according to claim 1 , wherein said processor comprises a very long instruction word (VLIW) architecture.
5 . The apparatus according to claim 1 , further comprising a single decoder configured to generate one or more decoded instructions by decoding execution sets.
6 . The apparatus according to claim 5 , wherein said decoded instructions are dispatched from said decoder to a plurality of execution units.
7 . The apparatus according to claim 1 , wherein each of said predefined prefix codes reduce a penalty in execution of a conditional change of flow (COF) by a digital signal processor (DSP) core.
8 . The apparatus according to claim 7 , wherein said first predetermined prefix code reduces a penalty of fetching from memory.
9 . The apparatus according to claim 7 , wherein said second predetermined prefix code reduces all change of flow penalty cycles.
10 . The apparatus according to claim 1 , wherein said apparatus is implemented as one or more integrated circuits.
11 . A method of control code parallelization through hardware treatment of data dependency, comprising the steps of:
buffering a plurality of fetch sets; and
performing a change of flow operation in a processor based upon at least one of (i) a comparison between addresses of two memory locations involved in each of two memory accessess, (ii) a first predefined prefix code, and (iii) a second predefined prefix code.
12 . The method according to claim 11 , wherein at least one of said fetch sets comprises a prefix word, said method further comprising:
selecting a dual path fetch operation of said processor in response to said prefix word containing said first predefined prefix code; and
selecting a dual path fetch and execute operation of said processor in response to said prefix word containing said second predefined prefix code.
13 . The method according to claim 11 , wherein each of said fetch sets comprises a variable length execution set.
14 . The method according to claim 11 , wherein said processor comprises a very long instruction word (VLIW) architecture.
15 . The method according to claim 11 , further comprising:
generating one or more decoded instructions by decoding execution sets using a single decoder configured.
16 . The method according to claim 15 , wherein said decoded instructions are dispatched from said decoder to a plurality of execution units of said processor.
17 . The method according to claim 11 , wherein said processor comprises a digital signal processor (DSP) core and each of said predefined prefix codes reduce a penalty in execution of a conditional change of flow (COF) instruction.
18 . The method according to claim 17 , wherein said first predetermined prefix code reduces a penalty of fetching from memory.
19 . The method according to claim 17 , wherein said second predetermined prefix code reduces all change of flow penalty cycles.
20 . An apparatus comprising:
means for storing a plurality of fetch sets; and
means for performing a change of flow operation based upon at least one of (i) a comparison between addresses of two memory locations involved in each of two memory accesses, (ii) a first predefined prefix code, and (iii) a second predefined prefix code.