IP Library Granted Patent US 8,824,667
Granted Patent B2
US 8,824,667 · App. 13/222,050 · Granted Sep 2, 2014

Time-domain acoustic echo control

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Quick Facts
Patent No.
US 8,824,667
App. No.
13/222,050
Granted
Sep 2, 2014
Kind
B2
Abstract

In one embodiment, an acoustic echo control (AEC) module receives an outgoing signal and an incoming signal, which, at various times, contains acoustic echo corresponding to the outgoing signal. The AEC module has a delay estimation block that estimates, in the time domain, the echo delay using an adaptive filtering technique. This delay estimation is used to align samples of the incoming signal having acoustic echo with the corresponding samples of the outgoing signal from which the acoustic echo originated. The AEC module determines whether or not samples of the incoming signal contain acoustic echo based on the aligned outgoing signal, and the determinations are applied to a hangover counter. The AEC module then suppresses acoustic echo in the incoming signal and adds comfort noise to the incoming signal. The amount of echo suppression performed is gradually increased or decreased based on comparisons of the counter to a hangover threshold.

Claims (71)

1. A processor-implemented method for processing a signal, the method comprising:

(a) generating, in a time domain, a gain value corresponding to how much acoustic echo to suppress in the signal, wherein step (a) comprises:

(a1) generating a counter value indicating how long acoustic echo has been detected in the signal without a detection of doubletalk;

(a2) comparing the counter value to a specified counter threshold value; and

(a3) adjusting the gain value based on the comparison of step (a2); and

(b) applying the gain value to the signal in the time domain.

2. The processor-implemented method of claim 1 , wherein step (a3) comprises:

(a3i) decreasing the gain value towards zero if the counter value is determined to be greater than the specified counter threshold value; and

(a3ii) increasing the gain value towards one if the counter value is determined to be less than the specified counter threshold value.

3. The processor-implemented method of claim 1 , wherein step (a1) comprises:

(a1i) generating an echo return loss (ERL) value for the signal;

(a1ii) comparing the ERL value to a specified ERL threshold value;

(a1iii) generating a signal-level value for the signal;

(a1iv) comparing the signal-level value to a specified signal-level threshold value; and

(a1v) detecting that acoustic echo exists in the signal without detecting doubletalk based on (i) the comparison of step (a1ii) and (ii) the comparison of step (a1iv).

4. The processor-implemented method of claim 3 , wherein step (a1v) comprises detecting that acoustic echo exists in the signal without detecting doubletalk if (i) the ERL value is greater than the specified ERL threshold value and (ii) the signal-level value is greater than the specified signal-level threshold value.

5. The processor-implemented method of claim 1 , wherein:

the signal is an incoming signal received at near-end user equipment;

the acoustic echo is generated by a microphone of far-end user equipment based on sounds generated by a loudspeaker of the far-end user equipment based on an outgoing signal transmitted from the near-end user equipment to the far-end user equipment; and

step (a) comprises comparing the incoming signal to the outgoing signal in the time domain to determine how much acoustic echo to suppress in the incoming signal.

6. The processor-implemented method of claim 5 , wherein step (a) comprises:

(a1) determining, in the time domain, amount of delay in timing of the acoustic echo relative to timing of the outgoing signal;

(a2) delaying a copy of the outgoing signal by the determined amount of delay;

(a3) generating, in the time domain, an echo return loss (ERL) value based on (i) signal level of the delayed copy of the outgoing signal and (ii) signal level of the incoming signal; and

(a4) using the ERL value to determine, in the time domain, how much acoustic echo to suppress in the signal.

7. Apparatus comprising a processor adapted to process a signal, the apparatus comprising:

an acoustic echo detector adapted to generate, in a time domain, a gain value corresponding to how much acoustic echo to suppress in the signal, wherein the acoustic echo detector is adapted to:

generate a counter value indicating how long acoustic echo has been detected in the signal without a detection of doubletalk;

compare the counter value to a specified counter threshold value; and

adjust the gain value based on the comparison of the counter value to the specified counter threshold value; and

an acoustic echo controller adapted to apply the gain value to the signal in the time domain.

8. The apparatus of claim 7 , wherein the acoustic echo detector is adapted to:

decrease the gain value towards zero if the counter value is determined to be greater than the specified counter threshold value; and

increase the gain value towards one if the counter value is determined to be less than the specified counter threshold value.

9. The apparatus of claim 7 , wherein the acoustic echo detector is adapted to:

generate an echo return loss (ERL) value for the signal;

compare the ERL value to a specified ERL threshold value;

generate a signal-level value for the signal;

compare the signal-level value to a specified signal-level threshold value; and

detect that acoustic echo exists in the signal without detecting doubletalk based on (i) the comparison of the ERL value to the specified ERL threshold value and (ii) the comparison of the signal-level value to the specified signal-level threshold value.

10. The apparatus of claim 9 , wherein the acoustic echo detector is adapted to detect that acoustic echo exists in the signal without detecting doubletalk if (i) the ERL value is greater than the specified ERL threshold value and (ii) the signal-level value is greater than the specified signal-level threshold value.

11. The apparatus of claim 7 , wherein:

the signal is an incoming signal received at near-end user equipment;

the acoustic echo is generated by a microphone of far-end user equipment based on sounds generated by a loudspeaker of the far-end user equipment based on an outgoing signal transmitted from the near-end user equipment to the far-end user equipment; and

the acoustic echo detector is adapted to compare the incoming signal to the outgoing signal in the time domain to determine how much acoustic echo to suppress in the incoming signal.

12. The apparatus of claim 11 , wherein the acoustic echo detector is adapted to:

determine, in the time domain, amount of delay in timing of the acoustic echo relative to timing of the outgoing signal;

delay a copy of the outgoing signal by the determined amount of delay;

generate, in the time domain, an echo return loss (ERL) value based on (i) signal level of the delayed copy of the outgoing signal and (ii) signal level of the incoming signal; and

use the ERL value to determine, in the time domain, how much acoustic echo to suppress in the signal.

13. The apparatus of claim 7 , wherein the apparatus is an integrated circuit.

14. A processor-implemented method for processing a signal, the method comprising:

(a) determining, in a time domain, how much acoustic echo to suppress in the signal; and

(b) processing the signal in the time domain based on the determination of how much acoustic echo to suppress, wherein:

the signal is an incoming signal received at near-end user equipment;

the acoustic echo is generated by a microphone of far-end user equipment based on sounds generated by a loudspeaker of the far-end user equipment based on an outgoing signal transmitted from the near-end user equipment to the far-end user equipment; and

step (a) comprises comparing the incoming signal to the outgoing signal in the time domain to determine how much acoustic echo to suppress in the incoming signal, wherein step (a) comprises:

(a1) determining, in the time domain, amount of delay in timing of the acoustic echo relative to timing of the outgoing signal;

(a2) delaying a copy of the outgoing signal by the determined amount of delay;

(a3) generating, in the time domain, an echo return loss (ERL) value based on (i) signal level of the delayed copy of the outgoing signal and (ii) signal level of the incoming signal; and

(a4) using the ERL value to determine, in the time domain, how much acoustic echo to suppress in the signal.

15. Apparatus comprising a processor adapted to process a signal, the apparatus comprising:

an acoustic echo detector adapted to determine, in a time domain, how much acoustic echo to suppress in the signal; and

an acoustic echo controller adapted to process the signal in the time domain based on the determination of how much acoustic echo to suppress in the signal, wherein:

the signal is an incoming signal received at near-end user equipment;

the acoustic echo is generated by a microphone of far-end user equipment based on sounds generated by a loudspeaker of the far-end user equipment based on an outgoing signal transmitted from the near-end user equipment to the far-end user equipment; and

the acoustic echo detector is adapted to compare the incoming signal to the outgoing signal in the time domain to determine how much acoustic echo to suppress in the incoming signal, wherein the acoustic echo detector is adapted to:

determine, in the time domain, amount of delay in timing of the acoustic echo relative to timing of the outgoing signal;

delay a copy of the outgoing signal by the determined amount of delay;

generate, in the time domain, an echo return loss (ERL) value based on (i) signal level of the delayed copy of the outgoing signal and (ii) signal level of the incoming signal; and

use the ERL value to determine, in the time domain, how much acoustic echo to suppress in the signal.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded May 29, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION
Reel/Frame 035797/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2011
From: MAZURENKO, IVAN LEONIDOVICH; BABIN, DMITRY NIKOLAEVICH; PARFENOV, DENIS VASSILEVICH; PETYUSHKO, ALEXANDER ALEXANDROVICH; MARKOVIC, ALEXANDER
To: LSI CORPORATION
Reel/Frame 026834/0759 →