Controller and method for statistical allocation of multichannel direct memory access bandwidth
View Patent ↗A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and configured to provide request signals, priority signals and counter value signals representing current values of the counters at a given time and (2) a grant control unit coupled to the channel interfaces and configured to grant DMA access to one of the channel interfaces based on values of the priority signals and the counter value signals.
1. A DMA controller, comprising: channel interfaces including respective counters which represent a priority of a corresponding channel and configured to provide request signals, priority signals and counter value signals representing current values of said counters at a given time; and a grant control unit coupled to said channel interfaces and configured to grant DMA access to one of said channel interfaces based on values of said priority signals and said counter value signals; said grant control unit including a priority select module configured to receive and select among said priority signals based on ratios of each of said values of said priority signals to said sum of said counter value signals corresponding to active ones of said channel interfaces.
2. The DMA controller as recited in claim 1 wherein said grant control unit includes a multiplexer configured to receive and select among said request signals.
3. The DMA controller as recited in claim 1 wherein said grant control unit includes an adder configured to receive and add at least some values of said counter value signals.
4. The DMA controller as recited in claim 3 wherein said adder is configured to add only said values of said counter value signals corresponding to active ones of channels.
5. The DMA controller as recited in claim 1 wherein said priority select module is further configured to select among said priority signals based on values thereof and a mathematical function of said counter value signals.
6. The DMA controller as recited in claim 1 wherein said grant control unit is configured to cause a counter associated with said one of said channel interfaces to decrement upon said granting of said DMA access.
7. The DMA controller as recited in claim 1 wherein said counters are further configured to receive a reset signal from said grant control unit and respond thereto by assuming an initial value representing a priority.
8. The DMA controller as recited in claim 1 wherein said priority select module is configured to grant said DMA access using sequential execution.
9. The DMA controller as recited in claim 1 wherein said priority select module is configured to grant said DMA access using nonsequential execution.
10. A method of statistically allocating multichannel DMA bandwidth, comprising: providing request signals, priority signals and counter value signals representing current values for counters which represent a priority of a corresponding channel of channel interfaces at a given time; granting DMA access to one of said channel interfaces based on values of said priority signals and said counter value signals, wherein said granting includes selecting among said priority signals based on ratios of each of said values of said priority signals to said sum of said counter value signals corresponding to active ones of said channel interfaces.
11. The method as recited in claim 10 further comprising selecting among said request signals.
12. The method as recited in claim 10 further comprising adding at least some values of said counter value signals.
13. The DMA controller as recited in claim 12 further comprising adding only said values of said counter value signals corresponding to active ones of channels.
14. The method as recited in claim 10 wherein said granting includes selecting among said priority signals based on values thereof and a mathematical function of said counter value signals.
15. The method as recited in claim 10 further comprising causing a counter associated with said one of said channel interfaces to decrement upon said granting of said DMA access.
16. The method as recited in claim 10 further comprising responding, with said counters, to a reset signal unit by assuming an initial value representing a priority.
17. The method as recited in claim 10 further comprising granting said DMA access using sequential execution.
18. The method as recited in claim 10 further comprising granting said DMA access using nonsequential execution.