Orthogonal variable spreading factor code sequence generation

1. An apparatus comprising:

a first circuit configured to generate (i) a plurality of first code bits in response to an index value and (ii) a plurality of first intermediate bits in response to said index value, wherein (a) said first code bits are generated in parallel with said first intermediate bits, (b) said first code bits are generated separately from said first intermediate bits and (c) said first code bits are fewer in number than said first intermediate bits; and

a second circuit configured to generate a plurality of second code bits in response to all of (i) said index value, (ii) said first code bits and (iii) said first intermediate bits, wherein a combination of said first code bits and said second code bits forms one of a plurality of orthogonal codes.

2. The apparatus according to claim 1 , wherein said orthogonal codes comprises orthogonal variable spreading factor codes.

3. The apparatus according to claim 1 , wherein a delay from a reception of said index value through said generation of said one orthogonal code is at most three logic gate delays.

4. The apparatus according to claim 1 , wherein (a) said second circuit is further configured to generate a plurality of second intermediate bits in response to both (i) said index value and (ii) said first intermediate bits and (b) said second code bits are greater in number than said second intermediate bits.

5. The apparatus according to claim 4 , wherein said second intermediate bits are generated in parallel with said second code bits.

6. The apparatus according to claim 4 , further comprising a third circuit configured to generate a plurality of third code bits in response to all of (i) said index value, (ii) said first code bits, (iii) said first intermediate bits and (iv) said second intermediate bits, wherein a combination of said first code bits, said second code bits and said third code bits forms another one of said orthogonal codes.

7. The apparatus according to claim 4 , wherein a delay from a reception of said index value through said generation of said one orthogonal code is at most four logic gate delays.

8. The apparatus according to claim 6 , wherein said first code bits are 4 code bits, said second code bits are 12 code bits and said third code bits are 240 code bits.

9. The apparatus according to claim 1 , wherein said first circuit and said second circuit form a portion of a wideband code division multiple access circuit.

10. The apparatus according to claim 1 , wherein said apparatus is implemented as one or more integrated circuits.

11. A method for orthogonal code generation, comprising the steps of:

(A) generating a plurality of first code bits in response to an index value;

(B) generating a plurality of first intermediate bits in response to said index value, wherein (i) said first code bits are generated in parallel with said first intermediate bits, (ii) said first code bits are generated separately from said first intermediate bits and (iii) said first code bits are fewer in number than said first intermediate bits; and

(C) generating a plurality of second code bits in response to all of (i) said index value, (ii) said first code bits and (iii) said first intermediate bits, wherein a combination of said first code bits and said second code bits forms one of a plurality of orthogonal codes.

12. The method according to claim 11 , wherein said orthogonal codes comprises orthogonal variable spreading factor codes.

13. The method according to claim 11 , wherein a delay from a reception of said index value through said generation of said one orthogonal code is at most three logic gate delays.

14. The method according to claim 11 , further comprising the step of:

generating a plurality of second intermediate bits in response to both (i) said index value and (ii) said first intermediate bits, wherein said second code bits are greater in number than said second intermediate bits.

15. The method according to claim 14 , wherein said second intermediate bits are generated in parallel with said second code bits.

16. The method according to claim 14 , further comprising the step of:

generating a plurality of third code bits in response to all of (i) said index value, (ii) said first code bits, (iii) said first intermediate bits and (iv) said second intermediate bits, wherein a combination of said first code bits, said second code bits and said third code bits forms another one of said orthogonal codes.

17. The method according to claim 14 , wherein a delay from a reception of said index value through said generation of said one orthogonal code is at most four logic gate delays.

18. The method according to claim 16 , wherein said first code bits are 4 code bits, said second code bits are 12 code bits and said third code bits are 240 code bits.

19. The method according to claim 11 , wherein said one orthogonal code is generated only in hardware.

20. An apparatus comprising:

means for generating a plurality of first code bits in response to an index value;

means for generating a plurality of first intermediate bits in response to said index value, wherein (i) said first code bits are generated in parallel with said first intermediate bits, (ii) said first code bits are generated separately from said first intermediate bits and (iii) said first code bits are fewer in number than said first intermediate bits; and

means for generating a plurality of second code bits in response to all of (i) said index value, (ii) said first code bits and (iii) said first intermediate bits, wherein a combination of said first code bits and said second code bits forms one of a plurality of orthogonal codes.