Cipher block chaining mode in encryption/decryption processing
View Patent ↗A data encryption/decryption circuit is presented that can be implemented in a field programmable gate array. First and second logic components are provided which are controlled by first and second control signal to direct data between memory and a data processing core (e.g., a DES or TDES processing core). In a ECB mode of operation, the logic components simply pass the data from the memory to the data processing core and from the data processing core to the memory. In CBC mode, the data from the memory is XORed with data from the appropriate data processing core in the first logic component during an encryption operation, and in the second logic component during a decryption operation.
1. A circuit to perform at least one of an encryption and a decryption operation on data, comprising:
a logic component configured to receive data from a memory, data from a data processing core, and a control signal;
wherein said logic component comprises an AND gate to receive said control signal and said data from the data processing core and an XOR gate to receive said data from the memory and an output of said AND gate; the logic gate being configured to output one of
said data from the memory and
an Exclusive OR combination of said data from the memory and said data from the data processing core based on said control signal.
2. The circuit of claim 1 wherein said logic component is a look-up table in a field programmable gate array.
3. The circuit of claim 2 wherein said data processing core is one of a Data Encryption Standard core and a Triple Data Encryption Standard core.
4. The circuit of claim 1 wherein said data processing core is one of a Data Encryption Standard core and a Triple Data Encryption Standard core.
5. A circuit to perform at least one of an encryption and a decryption operation on data, comprising:
a storage device to receive data from a memory; and
a logic component to receive said data from the storage device, data from a data processing core and a control signal, the logic component comprising an AND gate to receive said control signal and said data from the storage device and an XOR gate to receive said data from the data processing core and an output of said AND gate; wherein said logic component is to output one of said data from the data processing core and an Exclusive OR combination of said data from the data processing core and said data from the storage device.
6. The circuit of claim 5 wherein said logic component is a look-up table in a field programmable gate array.
7. The circuit of claim 6 wherein said data processing core is one of a Data Encryption Standard core and a Triple Data Encryption Standard core.
8. The circuit of claim 5 wherein said data processing core is one of a Data Encryption Standard core and a Triple Data Encryption Standard core.
9. A circuit to perform at least one of an encryption and a decryption operation on data comprising:
a first logic component to receive data from a memory, data from a data processing core, and a first control signal; wherein said first logic component comprises a first AND gate to receive said first control signal and said data from the data processing core and a first XOR gate to receive said data from the memory and an output of said first AND gate, the first logic component being configured to output one of said data from the memory and an Exclusive OR combination of said data from the memory and said data from the data processing core based on said first control signal;
a storage device to receive data from a memory; and
a second logic component to receive said data from the storage device, data from a data processing core and a second control signal; wherein said second logic component comprises a second AND gate to receive said second control signal and said data from the storage device and a second XOR gate to receive said data from the data processing core and an output of said second AND gate, the second logic component being configured to output one of said data from the data processing core and an Exclusive OR combination of said data from the data processing core and said data from the storage device.
10. The circuit of claim 9 wherein said each of said first and second logic components is a look-up table in a field programmable gate array.
11. The circuit of claim 9 wherein said storage device is a flip-flop in a field programmable gate array.
12. The circuit of claim 11 wherein said data processing core is one of a Data Encryption Standard core and a Triple Data Encryption Standard core.
13. The circuit of claim 9 wherein said data processing core is one of a Data Encryption Standard core and a Triple Data Encryption Standard core.
14. A method of performing at least one of an encryption and a decryption operation on data, comprising:
transmitting data from a memory to a first logic component;
transmitting data from a data processing core to said first logic component, the first logic component comprising an AND gate to receive a control signal and said data from the memory and an XOR gate to receive said data from the data processing core and an output of said AND gate; and
outputting one of said data from the memory and an Exclusive OR combination of said data from the memory and said data from the data processing core to said data processing core.
15. The method of claim 14 wherein said outputting operation to said data processing core is based on a first control signal.
16. The method of claim 15 further comprising: transmitting said data from the memory to a storage device; transmitting data from the storage device to a second logic component; transmitting said data from the data processing core to said second logic component; and outputting one of said data from the data processing core and an Exclusive OR combination of said data from the data processing core and said data from the storage device to said memory.
17. The method of claim 16 wherein said outputting operation to said memory is bases on a second control signal.