Low access time indirect memory accesses
View Patent ↗An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address.
1. An apparatus comprising:
a memory; and
a controller configured to (i) receive a read request from a processor, said read request comprising a first value and a second value, (ii) where said read request is an indirect memory access, (a) present said first value to said memory as a first address, (b) read address data stored in said memory at said first address and (c) generate a second address in response to a combination of said second value and said address data, (iii) where said read request is a direct memory access, generate said second address by copying said second value and (iv) read a requested data stored in said memory at said second address.
2. The apparatus according to claim 1 , wherein said controller is further configured to transfer said requested data to said processor to fulfill said read request.
3. The apparatus according to claim 1 , wherein said read request further comprises a third value.
4. The apparatus according to claim 3 , wherein (i) said controller is further configured to shift said address data by said third value and (ii) said second address is generated by adding said second value to said address data as shifted in response to said indirect memory access.
5. The apparatus according to claim 1 , wherein said controller is further configured to determine that said read request is either said direct memory access or said indirect memory access.
6. The apparatus according to claim 5 , wherein said first value determines said direct memory access or said indirect memory access.
7. The apparatus according to claim 1 , wherein said read request further comprises a flag that determines said direct memory access or said indirect memory access.
8. The apparatus according to claim 1 , wherein said indirect memory access is completed in response to only one request from said processor.
9. The apparatus according to claim 1 , wherein (i) said second value is a pointer to a base address of an array in said memory and (ii) said requested data is stored in said array at an offset from said base address in response to said indirect memory access.
10. The apparatus according to claim 1 , wherein said apparatus is implemented as one or more integrated circuits.
11. An apparatus comprising:
means for storing;
means for receiving a read request from a processor, said read request comprising a first value and a second value;
means for generating addresses configured to (i) present said first value to said means for storing as a first address, (ii) read address data stored in said means for storing at said first address, and (iii) generate a second address in response to a combination of said second value and said address data where said read request is an indirect memory access;
means for generating said second address by copying said second value where said read request is a direct memory access; and
means for reading a requested data stored in said means for storing at said second address.
12. A method for low access time indirect memory accesses, comprising the steps of:
(A) receiving a read request at a controller from a processor, said read request comprising a first value and a second value;
(B) where said read request is an indirect memory access,
(i) presenting said first value to a memory as a first address,
(ii) reading address data stored in said memory at said first address, and
(iii) generating a second address in response to a combination of said second value and said address data;
(C) where said read request is a direct memory access, generating said second address by copying said second value; and
(D) reading a requested data stored in said memory at said second address to said controller.
13. The method according to claim 12 , further comprising the step of:
transferring said requested data to said processor to fulfill said read request.
14. The method according to claim 12 , wherein said read request further comprises a third value.
15. The method according to claim 14 , further comprising the step of:
shifting said address data by said third value, wherein said second address is generated by adding said second value to said address data as shifted in response to said indirect memory access.
16. The method according to claim 12 , further comprising the step of:
determining that said read request is either said direct memory access or said indirect memory access using said controller.
17. The method according to claim 16 , wherein said first value determines said direct memory access or said indirect memory access.
18. The method according to claim 12 , wherein said read request further comprises a flag that determines said direct memory access or said indirect memory access.
19. The method according to claim 12 , wherein said indirect memory access is completed in response to only one request from said processor.
20. The method according to claim 12 , wherein (i) said second address is a pointer to a base address of an array in said memory and (ii) said requested data is stored in said array at an offset from said base address in response to said indirect memory access.