Digital signal processor having instruction set with an exponential function using reduced look-up table

1. A method performed by a vector-based digital signal processor for evaluating a non-linear exponential function for an input vector, x, said method comprising:

obtaining one or more software instructions;

in response to a predefined software instruction keyword for said non-linear exponential function, invoking at least one hardware functional unit that implements said non-linear exponential function to perform the following steps for each component of said input vector, x, to produce a corresponding component of an output vector in hardware, wherein said input vector, x, comprises a plurality of numbers and wherein said vector-based digital signal processor processes said plurality of numbers substantially simultaneously:

decomposing each component of said input vector, x, to an integer part, N, a first fractional part, q 1 , larger than a specified value, x 0 , and a second fractional part, q 2 , smaller than said specified value, x 0 ;

computing 2 q 2 using a polynomial approximation;

obtaining 2 q 1 from a look-up table in a random access memory (RAM) of said vector-based digital signal processor; and

evaluating said exponential function for said input vector, x, by multiplying 2 q 2 , and 2 q 1 together and performing a shift by N, wherein said predefined software instruction keyword for said non-linear exponential function is part of an instruction set of said vector-based digital signal processor.

2. The method of claim 1 , wherein said multiplying step comprises the step of first multiplying said values 2 q 2 and 2 q 1 together and said multiplication by 2 N is performed by shifting a result of said first multiplication by N bits.

3. The method of claim 1 , wherein said polynomial approximation is a cubic approximation.

4. The method of claim 1 , wherein 2 N is computed using a barrel shifter.

5. The method of claim 1 , wherein said vector-based digital signal processor executes software instructions from program code.

6. The method of claim 1 , wherein entries in said look-up table have a fewer number of bits than a number of bits in said input vector, x.

7. The method of claim 1 , wherein said polynomial approximation is a Taylor Series.

8. A vector-based digital signal processor that evaluates a non-linear exponential function for an input vector, x, comprising:

a memory storing at least one look-up table; and

at least one processor, coupled to the memory, operative to:

obtain one or more software instructions;

in response to a predefined software instruction keyword for said non-linear exponential function, invoke at least one hardware functional unit that implements said non-linear exponential function to perform the following steps for each component of said input vector, x, to produce a corresponding component of an output vector in hardware, wherein said input vector, x, comprises a plurality of numbers and wherein said vector-based digital signal processor processes said plurality of numbers substantially simultaneously:

decompose each component of said input vector, x, to an integer part, N, a first fractional part, q 1 , larger than a specified value, x 0 , and a second fractional part, q 2 , smaller than said specified value, x 0 ;

compute 2 q 2 using a polynomial approximation;

obtain 2 q 1 from at least one of said look-up tables in a random access memory (RAM) of said vector-based digital signal processor; and

evaluate said exponential function for said input vector, x, by multiplying 2 q 2 , and 2 q 1 together and performing a shift by N, wherein said predefined software instruction keyword for said non-linear exponential function is part of an instruction set of said vector-based digital signal processor.

9. The vector-based digital signal processor of claim 8 , wherein said multiplying step comprises the step of first multiplying said values 2 q 2 and 2 q 1 together and said multiplication by 2 N is performed by shifting a result of said first multiplication by N bits.

10. The vector-based digital signal processor of claim 8 , wherein said polynomial approximation is a cubic approximation.

11. The vector-based digital signal processor of claim 8 , wherein 2 N is computed using a barrel shifter.

12. The vector-based digital signal processor of claim 8 , wherein said digital signal processor executes software instructions from program code.

13. The vector-based digital signal processor of claim 8 , wherein entries in said first and second look-up tables have a fewer number of bits than a number of bits in said input vector, x.

14. The vector-based digital signal processor of claim 8 , wherein said polynomial approximation is a Taylor Series.

15. An integrated circuit, comprising:

a vector-based digital signal processor that evaluates a non-linear exponential function for an input vector, x, comprising:

a memory storing at least one look-up table; and

at least one processor, coupled to the memory, operative to:

obtain one or more software instructions;

in response to a predefined software instruction keyword for said non-linear exponential function, invoke at least one hardware functional unit that implements said non-linear exponential function to perform the following steps for each component of said input vector, x, to produce a corresponding component of an output vector in hardware, wherein said input vector, x, comprises a plurality of numbers and wherein said vector-based digital signal processor processes said plurality of numbers substantially simultaneously:

decompose each component of said input vector, x, to an integer part, N, a first fractional part, q 1 , larger than a specified value, x 0 , and a second fractional part, q 2 , smaller than said specified value, x 0 ;

compute 2 q 2 using a polynomial approximation;

obtain 2 q 1 from at least one of said look-up tables in a random access memory (RAM) of said vector-based digital signal processor; and

evaluate said exponential function for said input vector, x, by multiplying 2 q 2 , and 2 q 1 together and performing a shift by N, wherein said predefined software instruction keyword for said non-linear exponential function is part of an instruction set of said vector-based digital signal processor.

16. The integrated circuit of claim 15 , wherein said multiplying step comprises the step of first multiplying said values 2 q 2 and 2 q 1 together and said multiplication by 2 N is performed by shifting a result of said first multiplication by N bits.

17. The integrated circuit of claim 15 , wherein said polynomial approximation is a cubic approximation.

18. The integrated circuit of claim 15 , wherein 2 N is computed using a barrel shifter.

19. The integrated circuit of claim 15 , wherein said vector-based digital signal processor executes software instructions from program code.

20. The integrated circuit of claim 15 , wherein entries in said first and second look-up tables have a fewer number of bits than a number of bits in said input vector, x.

21. The integrated circuit of claim 15 , wherein said polynomial approximation is a Taylor Series.

22. A method performed by a vector-based digital signal processor for evaluating a non-linear exponential function for an input vector, x, having an initial basis, Z, said method comprising:

obtaining one or more software instructions;

in response to a predefined software instruction keyword for said non-linear exponential function, invoking at least one hardware functional unit that implements said non-linear exponential function to perform the following steps for each component of said input vector, x, to produce a corresponding component of an output vector in hardware, wherein said input vector, x, comprises a plurality of numbers and wherein said vector-based digital signal processor processes said plurality of numbers substantially simultaneously:

multiplying each component of said input vector, x, having said initial basis, Z, by logz(Y) to generate a modified input vector, x 1 , where log Z (Y), is obtained from a first look-up table in a random access memory (RAM) of said vector-based digital signal processor;

decomposing each component of said modified input vector, x 1 , to an integer part, N, a first fractional part, q 1 , larger than a specified value, x 0 , and a second fractional part, q 2 , smaller than said specified value, x 0 ;

computing Z q 2 using a polynomial approximation;

obtaining Z q 1 from a second look-up table in said random access memory (RAM) of said vector-based digital signal processor; and

evaluating said exponential function for said input vector, x, by multiplying Z q 2 , and Z q 1 together and performing a shift by N, wherein said predefined software instruction keyword for said non-linear exponential function is part of an instruction set of said vector-based digital signal processor.

23. The method of claim 22 , wherein said polynomial approximation is a cubic approximation.

24. The method of claim 22 , wherein said polynomial approximation is a Taylor Series.