Skip based control logic for first in first out buffer
View Patent ↗A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, and a read pointer for pointing to a read address of the storage for a read operation. Further, the FIFO buffer system includes a control logic for incrementing the read pointer based on a skip parameter of a skip register. The skip parameter is used to characterize a validity of the data for the read operation.
1. A first in and first out (FIFO) buffer system, comprising:
a storage device for storing data;
a write pointer for pointing to a write address of the storage device for a write operation;
a read pointer for pointing to a read address of the storage device for a read operation; and
a control logic for incrementing the read pointer based on a skip parameter of a skip register, wherein the skip parameter is used to characterize a validity of the data for the read operation, and wherein the skip register is a configurable register which enables skipping a number of locations for a read operation, wherein the control logic comprises a skip based control logic circuit for:
setting a current location of the read pointer to a current location of the write pointer if a value of the skip parameter is greater than zero and a data count of the data;
decreasing the value of the skip parameter by the data count; and,
setting the data count to zero.
2. The system of claim 1 , wherein the control logic comprises the skip based control logic circuit for performing the incrementing the read pointer by increasing the current location of the read pointer by the value of the skip parameter if the data count of the data is greater than the value of the skip parameter.
3. The system of claim 2 , wherein the increasing the current location of the read pointer by the value of the skip parameter further comprises decreasing the data count by the value of the skip parameter.
4. The system of claim 1 , wherein the control logic comprises the skip based control logic circuit operable for setting the read pointer by increasing the current location of the read pointer by one address location in the storage device if the skip parameter is a null value.
5. The system of claim 4 , wherein the increasing the current location of the read pointer by the one address location further comprises decreasing the data count by the one address location.
6. The system of claim 1 , wherein the setting the data count to zero further comprises performing another write operation with additional data.
7. The system of claim 6 , wherein the read pointer is set by increasing the current location of the read pointer by the value of the skip parameter if a size of the additional data is greater than the value of the skip parameter.
8. The system of claim 7 , wherein the increasing the current location of the read pointer by the value of the skip parameter further comprises decreasing the size of the additional data by the value of the skip parameter.
9. The system of claim 2 , wherein the skip based control logic circuit comprises two multiplexers and an adder coupled in series.
10. A method for a first in and first out (FIFO) buffer system, comprising:
storing data on a storage device;
pointing to a write address of the storage device for a write operation using a write pointer;
pointing to a read address of the storage device for a read operation using a read pointer;
incrementing the read pointer using a control logic based on a skip parameter of a skip register, wherein the skip parameter is used to characterize a validity of the data for the read operation, and wherein the skip register is a configurable register which enables skipping a number of locations for a read operation;
setting a current location of the read pointer to a current location of the write pointer if a value of the skip parameter is greater than zero and a data count of the data, wherein the control logic comprising a skip based control logic circuit sets the current location of the read pointer;
decreasing the value of the skip parameter by the data count using the skip based control logic circuit; and,
setting the data count to zero using the skip based control logic circuit.
11. The method of claim 10 , wherein incrementing the read pointer comprises increasing the current location of the read pointer by the value of the skip parameter if the data count of the data is greater than the value of the skip parameter, wherein the control logic comprising the skip based control logic circuit increases the current location of the read pointer.
12. The method of claim 11 , wherein the increasing the current location of the read pointer by the value of the skip parameter further comprises decreasing the data count by the value of the skip parameter.
13. The method of claim 10 , further comprising setting the read pointer by increasing the current location of the read pointer by one address location in the storage device if the skip parameter is a null value, wherein the control logic comprising the skip based control logic circuit sets the read pointer.
14. The method of claim 13 , wherein the increasing the current location of the read pointer by the one address location further comprises decreasing the data count by the one address location.
15. The method of claim 10 , wherein the setting the data count to zero further comprises performing another write operation with additional data.
16. The method of claim 15 , further comprising setting the read pointer by increasing the current location of the read pointer by the value of the skip parameter if a size of the additional data is greater than the value of the skip parameter.
17. The method of claim 16 , wherein the increasing the current location of the read pointer by the value of the skip parameter further comprises decreasing the size of the additional data by the value of the skip parameter.
18. A computer program stored on a non-transitory computer readable storage medium comprising instructions that, when executed by a computing platform, result in execution of a method for a first in and first out (FIFO) buffer system, comprising:
storing data on a storage device;
pointing to a write address of the storage device for a write operation using a write pointer;
pointing to a read address of the storage device for a read operation using a read pointer; and
incrementing the read pointer using a control logic based on a skip parameter of a skip register, wherein the skip parameter is used to characterize a validity of the data for the read operation, and wherein the skip register is a configurable register which enables skipping a number of locations for a read operation, wherein the control logic comprises a skip based control logic circuit for:
setting a current location of the read pointer to a current location of the write pointer if a value of the skip parameter is greater than zero and a data count of the data;
decreasing the value of the skip parameter by the data count; and,
setting the data count to zero.