Granted Patent B2

US 7,724,855 · App. 11/773,344 · Granted May 25, 2010

Abstract

Claims (38)

1. An event edge synchronization system, comprising:

a first clock zone device configured to generate an event signal, based upon a first clock rate, to indicate an event has occurred;

a second clock zone device configured to operate at a second clock rate, which is asynchronous with said first clock rate; and

a synchronous notification subsystem configured to receive a clock input of a single clock rate from said second clock zone device, wherein said single clock rate is said second clock rate, receive said event signal from said first clock zone device, synchronize said event signal to said second clock rate based upon an edge transition of said event signal and said second clock rate, and generate a synchronous notification signal therefrom, said synchronous notification subsystem including:

a first logic device configured to generate a first intermediate signal based upon said event signal and said single clock rate;

a second logic device configured to generate a second intermediate signal based upon said first intermediate signal and said single clock rate;

a third logic device configured to generate a third intermediate signal based upon said second intermediate signal and said single clock rate, wherein said third intermediate signal is not a complement of said second intermediate signal; and

a comparison logic device configured to generate said synchronous notification signal based upon said second and third intermediate signals, wherein said first, second and third intermediate signals mimic a data input of said first, second and third logic devices at timing transitions of said single clock rate.

2. The event edge synchronization system as recited in claim 1 wherein said first, second and third logic devices are “D” type flip-flops.

3. The event edge synchronization system as recited in claim 1 wherein said comparison logic device is an exclusive-OR (XOR) gate.

4. The event edge synchronization system as recited in claim 1 wherein said synchronous notification subsystem synchronizes said event signal to said second clock rate based upon a positive edge transition of said event signal.

5. The event edge synchronization system as recited in claim 1 wherein said event is re-transmission of a block of data of a buffer.

6. The event edge synchronization system as recited in claim 1 wherein said event signal transitions from a first signal condition to a second signal condition to indicate occurrence of said event.

7. The event edge synchronization system as recited in claim 6 wherein said event signal subsequently transitions from said second signal condition to said first signal condition to indicate occurrence of another event.

8. The event edge synchronization system as recited in claim 7 wherein said first signal condition is a low signal condition and said second signal condition is a high signal condition.

9. A method of operating an event edge synchronization system, comprising:

generating an event signal based upon a first clock rate associated with a first clock zone device to indicate an event has occurred;

operating a second clock zone device at a second clock rate, which is asynchronous with said first clock rate;

receiving said event signal from said first clock zone device and also receiving a clock input of a single clock rate from said second clock zone device, wherein said single clock rate is said second clock rate;

synchronizing said event signal to said second clock rate based upon an edge transition of said event signal and said second clock rate, said synchronizing including:

generating a first intermediate signal based upon said event signal and a clock signal associated with said second clock rate;

generating a second intermediate signal based upon said first intermediate signal and said clock signal associated with said second clock rate;

generating a third intermediate signal based upon said second intermediate signal and said clock signal associated with said second clock rate, wherein said third intermediate signal is not a complement of said second intermediate signal; and

generating a synchronous notification signal based upon said second and third intermediate signals, wherein said first, second and third intermediate signals mimic a data input of said first, second and third logic devices at timing transitions of said single clock rate.

10. The method as recited in claim 9 wherein said generating said first, second and third intermediate signals further comprises employing “D” type flip-flops.

11. The method as recited in claim 9 wherein said generating said synchronous notification signal further comprises employing an exclusive-OR (XOR) gate.

12. The method as recited in claim 9 wherein said synchronizing is based upon a positive edge transition of said event signal.

13. An event edge synchronization system, comprising:

means that generates an event signal based upon a first clock rate to indicate an event has occurred;

means that operates at a second clock rate, which is asynchronous with said first clock rate; and

notification means that receives said event signal based on said first clock rate and also receives a clock input of a single clock rate which is said second clock rate, synchronizes said event signal to said second clock rate based upon an edge transition of said event signal and said second clock rate, and generates a synchronous notification signal, said notification means including:

first means that generates a first intermediate signal based upon said event signal and a clock signal of said means that operates at a second clock rate;

second means that generates a second intermediate signal based upon said first intermediate signal and said clock signal of said means that operates at a second clock rate;

third means that generates a third intermediate signal based upon said second intermediate signal and said clock signal of said means that operates at a second clock rate, wherein said third intermediate signal is not a complement of said second intermediate signal; and

comparison means configured to generate said synchronous notification signal based upon said second and third intermediate signals, wherein said first, second and third intermediate signals mimic a data input of said first, second and third logic devices at timing transitions of said single clock rate.

14. The event edge synchronization system as recited in claim 13 wherein said first, second and third means employ “D” type flip-flops.

15. The event edge synchronization system as recited in claim 13 wherein said comparison means employs an exclusive-OR (XOR) gate.

16. The event edge synchronization system as recited in claim 13 wherein said notification means synchronizes said event signal to said second clock rate based upon a positive edge transition of said event signal.

Assignments (7)