Packet data processor in a communications processor architecture
View Patent ↗Described embodiments provide a network processor having a hardware accelerator that identifies a received packet and, based on a flow identification associated with the received packet, might pre-fetch pre-established portions of data from the received packet into local data memory (e.g., local data cache) for processing by a general purpose processor core. In addition to the packet data, the software necessary for the general-purpose processor core to process the data might also be pre-fetched into local instruction memory (e.g., local instruction cache). The flow identification might be used to select different portions of the packet and different software to be pre-fetched.
1. A network processor comprising:
a shared memory;
an input/output module arranged on a ring bus to communicate tasks from a source to a destination on the ring bus, the input/output module to receive a packet and store the received packet in the shared memory;
a packet processing module arranged on the ring bus; and
a processor core arranged on the ring bus and having a local memory;
wherein the packet processing module to:
classify the received packet stored in the shared memory,
identify which flow of one or more of known flows the received packet pertains to,
retrieve structural metadata corresponding to the identified flow of the received packet, and pass the structural metadata to the processor core, wherein the structural metadata is retrieved from at least one configuration table corresponding to the identified flow out of a plurality of configuration tables, and includes one of at least an offset and length of the received packet for determining what addresses in the shared memory are to be pre-fetched to obtain the portion of packet data of the received packet and an identifying address and length of the software instructions in the shared memory to be pre-fetched; and
wherein the processor core to:
pre-fetch content at address locations in the shared memory specified by the structural metadata,
store the pre-fetched content into the local memory, and
process the pre-fetched content stored in the local memory,
wherein the pre-fetched content comprises (i) at least a portion of packet data of the received packet, and (ii) software instructions corresponding to the identified flow, which are used to process the packet data.
2. The network processor of claim 1 wherein the local memory has a data portion and an instruction portion, wherein the pre-fetched packet data is stored in the data portion of the local memory, and wherein the pre-fetched software instructions are stored in the instruction portion of the local memory.
3. The network processor of claim 1 wherein when the packet processing module identifies which flow the received packet pertains to, the packet processing module returns a flow identifier associated with the identified flow, and the structural metadata is retrieved by the packet processing module using the flow identifier to identify the retrieved structural metadata.
4. The network processor of claim 3 wherein the structural metadata is stored in the shared system memory.
5. The network processor of claim 1 wherein the packet processing module classifies the stored packet by port number, matching bit patterns of the stored packet to patterns of known protocols, frequency analysis of bytes in the stored packet statistical analysis of packet sizes, statistical analysis of packet inter-arrival times, or a combination thereof.
6. The network processor of claim 1 wherein if the packet processing module is unable to classify the stored packet as pertaining to one of the known flows, then the packet processing module assigns a new flow to the received packet and a default set of structural metadata is passed to the processor core module.
7. The network processor of claim 1 wherein the configuration table is stored in the packet processing module.
8. The network processor of claim 1 wherein the local memory includes a cache memory.
9. The network processor of claim 1 wherein the network processor is implemented in an integrated circuit.
10. A method of processing one or more packets received by a network processor having at least one shared system memory, the method comprising:
receiving a packet by an input/output module which is arranged on a ring bus that communicates tasks from a source to a destination on the ring bus;
storing, by the input/output module and a switch, the received packet in the shared system memory;
pre-programming, by the processor core module, one or more configuration tables to include structural metadata corresponding to one or more known flows;
classifying, by a packet processing module, the received packet stored in the shared system memory, to identify which flow of the one or more known flows the received packet pertains to;
retrieving, by the packet processing module, structural metadata corresponding to the identified flow of the received packet, wherein the structural metadata is retrieved from at least one configuration table of the one or more configuration tables, which corresponds to the identified flow, and includes one of at least an offset and length of the received packet for determining what addresses in the shared memory are to be pre-fetched to obtain the portion of packet data of the received packet and an identifying address and length of the software instructions in the shared memory to be pre-fetched;
passing, to a processor core module using the ring bus, the structural metadata;
prefetching, by the processor core module, content at addresses in the shared memory specified by the structural metadata; and
storing the pre-fetched content into a memory local to the processor core module, wherein the pre-fetched content comprises (i) at least a portion of packet data of the received packet, and (ii) software instructions corresponding to the identified flow, which are used to process the packet data.
11. The method of claim 10 wherein the step of classifying is performed by port number, matching bit patterns of the stored packet to patterns of known protocols, frequency analysis of bytes in the stored packet, statistical analysis of packet sizes, statistical analysis of packet inter-arrival times, or a combination thereof.
12. The method of claim 10 wherein if the packet processing module is unable to classify the received packet as pertaining to one of the known flows, then the packet processing module assigns a new flow to the received packet and a default set of structural metadata is passed to the processor core module.
13. The method of claim 10 wherein in the classifying step, the packet processing module returns a flow identifier associated with the identified flow, and wherein the structural metadata is retrieved using the flow identifier to identify the retrieved structural metadata.
14. The method of claim 10 further comprising the step of: processing, by the processor core module using the pre-fetched software instructions in the local memory, the pre-fetched data stored in the local memory.
15. The method of claim 14 wherein the local memory has a data portion and an instruction portion, the pre-fetched packet data is stored in the data portion of the local memory, and the pre-fetched software instructions are stored in the instruction portion of the local memory.
16. The method of claim 10 wherein the local memory includes a cache memory.