Patent Assignment
Reel/Frame 033102/0270
CHANGE OF NAME
Recorded: 2014-06-06
Received: 2014-06-06
Pages: 90
Assignor
LSI LOGIC CORPORATION
Executed: 2007-04-06
Assignee
LSI CORPORATION
1320 RIDDER PARK DRIVE, SAN JOSE, CA, 95131, UNITED STATES
Covered Applications
(100)
METHOD CHARACTERIZING MATERIALS FOR A TRENCH ISOLATION STRUCTURE HAVING LOW TRENCH PARASITIC CAPACITANCE
App. No. 12/574,426
→
BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS
App. No. 12/574,479
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APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW
App. No. 12/140,773
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BASIC CELL ARCHITECTURE FOR STRUCTURED APPLICATION-SPECIFIC INTEGRATED CIRCUITS
App. No. 12/139,974
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FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES
App. No. 12/121,363
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METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT DESIGN FOR STATIC TIMING ANALYSIS
App. No. 12/117,760
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METHOD AND SYSTEM OF A SHARED BUS ARCHITECTURE
App. No. 12/045,036
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ENHANCED RAID LEVEL 3
App. No. 12/033,029
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FLEXIBLE HARDWARE ARCHITECTURE FOR ECC/HECC BASED CRYTOGRAPHY
App. No. 11/999,211
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INTEGRATED CIRCUIT PACKAGE WITH SPUTTERED HEAT SINK FOR IMPROVED THERMAL PERFORMANCE
App. No. 11/772,267
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INTEGRATED CIRCUIT WITH INDUCTOR HAVING HORIZONTAL MAGNETIC FLUX LINES
App. No. 11/811,519
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HIGH THROUGHPUT PIPELINED DATA PATH
App. No. 11/754,294
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EFFICIENT HARDWARE IMPLEMENTATION OF TWEAKABLE BLOCK CIPHER
App. No. 11/741,865
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ENHANCING PERFORMANCE OF SATA DISK DRIVES IN SAS DOMAINS
App. No. 11/733,132
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MEMORY DATA INVERSION ARCHITECTURE FOR MINIMIZING POWER CONSUMPTION
App. No. 11/696,870
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METHODS, APPARATUS, AND SYSTEMS FOR DETERMINING 1T STATE METRIC DIFFERENCES IN AN NT IMPLEMENTATION OF A VITERBI DECODER
App. No. 11/696,300
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REFERENCE VOLTAGE SHIFTING TECHNIQUE FOR OPTIMIZING SNR PERFORMANCE IN PIPELINE ADCS WITH RESPECT TO INPUT SIGNAL
App. No. 11/693,618
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METHODS AND STRUCTURES FOR TESTING SAS-2 SPEED OPTIONS IN SPEED NEGOTIATION WINDOWS
App. No. 11/691,240
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METHODS AND STRUCTURES FOR TESTING SAS TRANSCEIVER TRAINING OPTIONS IN SAS-2 TRAINING WINDOWS
App. No. 11/691,195
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ZERO-PENALTY RAID CONTROLLER MEMORY LEAK DETECTION AND ISOLATION METHOD AND SYSTEM UTILIZING SEQUENCE NUMBERS
App. No. 11/715,680
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APPARATUS AND METHODS FOR MULTIPLE UNIDIRECTIONAL VIRTUAL CONNECTIONS AMONG SAS DEVICES
App. No. 11/682,798
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STORAGE SYSTEM MANAGEMENT BASED ON A BACKUP AND RECOVERY SOLUTION EMBEDDED IN THE STORAGE SYSTEM
App. No. 11/713,205
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APPARATUS AND METHODS FOR CLUSTERING MULTIPLE INDEPENDENT PCI EXPRESS HIERARCHIES
App. No. 11/680,366
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METHOD AND/OR APPARATUS FOR COLOR SPACE REDUCTION FOR TRANSCODING SUBPICTURE ELEMENTS
App. No. 11/712,113
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LOW POWER DECISION FEEDBACK EQUALIZATION (DFE) THROUGH APPLYING DFE DATA TO INPUT DATA IN A DATA LATCH
App. No. 11/709,568
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SEQUENTIAL TESTER FOR LONGEST PREFIX SEARCH ENGINES
App. No. 11/706,943
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PIPELINED LDPC ARITHMETIC UNIT
App. No. 11/626,400
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SYSTEM AND METHOD OF VOLUME GROUP CREATION BASED ON AN AUTOMATIC DRIVE SELECTION SCHEME
App. No. 11/654,056
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RELIABLE AND EFFICIENT DATA TRANSFER OVER SERIAL PORT
App. No. 11/654,311
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HIERARCHY OF A STRUCTURE OF A VOLUME
App. No. 11/654,272
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SYSTEM AND METHOD FOR COMPENSATING FOR PVT VARIATION EFFECTS ON THE DELAY LINE OF A CLOCK SIGNAL
App. No. 11/643,492
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EFFICIENT 8X8 CABAC RESIDUAL BLOCK TRANSCODE SYSTEM
App. No. 11/643,642
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LOW COMPLEXITY LDPC ENCODING ALGORITHM
App. No. 11/613,256
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LOW AREA ARCHITECTURE IN BCH DECODER
App. No. 11/613,529
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METHOD AND SYSTEM FOR INTERLEAVING FIRST AND SECOND HALVES OF A DATA SEGMENT OF UNKNOWN LENGTH
App. No. 11/642,322
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METHOD AND APPARATUS FOR BOOTING INDEPENDENT OPERATING SYSTEMS IN A MULTI-PROCESSOR CORE INTEGRATED CIRCUIT
App. No. 11/642,045
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ELECTRONIC COMPONENT CONNECTION SUPPORT STRUCTURES INCLUDING AIR AS A DIELECTRIC
App. No. 11/641,989
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POLYMORPHIC MANAGEMENT OF EMBEDDED DEVICES USING WEB INTERFACES
App. No. 11/640,551
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Real time elastic FIFO latency optimization
App. No. 11/637,592
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OPTIMIZATION OF FLIP FLOP INITIALIZATION STRUCTURES WITH RESPECT TO DESIGN SIZE AND DESIGN CLOSURE EFFORT FROM RTL TO NETLIST
App. No. 11/634,683
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Band-pass high-order analog filter backed hybrid receiver equalization
App. No. 11/634,645
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WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O
App. No. 11/565,701
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PARALLEL LDPC DECODER
App. No. 11/565,670
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METHODS AND SYSTEMS FOR INTEGRATING UNIQUE INFORMATION IN SAS INTERFACE COMPONENTS
App. No. 11/562,228
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CIRCUIT, SYSTEMS AND METHODS FOR MONITORING STORAGE CONTROLLER STATUS
App. No. 11/562,207
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SAS ZONE GROUP PERMISSION TABLE VERSION IDENTIFIERS
App. No. 11/562,189
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BUILT IN SELF TEST TRANSPORT CONTROLLER ARCHITECTURE
App. No. 11/557,513
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SYSTEMS AND METHODS FOR IMPROVED PRODUCT VARIANT CONFIGURATION AND DISTRIBUTION IN HUB-BASED DISTRIBUTION
App. No. 11/554,673
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SYSTEM FOR INTERLEAVED STORAGE OF VIDEO DATA
App. No. 11/588,087
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Clock generation with minimum number of crystals in a multimedia system
App. No. 11/545,406
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SYSTEM AND METHOD FOR CONNECTING SAS RAID CONTROLLER DEVICE CHANNELS ACROSS REDUNDANT STORAGE SUBSYSTEMS
App. No. 11/545,872
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APPARATUS AND METHODS FOR IMPROVED SATA DEVICE INTERACTION WITHOUT A SAS EXPANDER
App. No. 11/538,900
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DEVICE FOR AVOIDING TIMING VIOLATIONS RESULTING FROM PROCESS DEFECTS IN A BACKFILLED METAL LAYER OF AN INTEGRATED CIRCUIT
App. No. 11/538,187
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Method and apparatus for managing virtual team collaboration meetings
App. No. 11/527,153
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FAILURE ANALYSIS VEHICLE FOR YIELD ENHANCEMENT WITH SELF TEST AT SPEED BURNIN CAPABILITY FOR RELIABILITY TESTING
App. No. 11/527,108
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LOW MUTUAL INDUCTANCE MATCHED INDUCTORS
App. No. 11/534,340
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APPARATUS AND METHOD OF MANUFACTURE FOR INTEGRATED CIRCUIT AND CMOS DEVICE INCLUDING EPITAXIALLY GROWN DIELECTRIC ON SILICON CARBIDE
App. No. 11/524,107
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SYSTEM AND METHOD FOR PROVIDING SWAP PATH VOLTAGE AND TEMPERATURE COMPENSATION
App. No. 11/523,139
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STABILIZATION FOR RANDOM CHIP IDENTIFIER CIRCUIT
App. No. 11/530,518
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IDENTIFICATION OF UNCOMMITTED MEMORY BLOCKS DURING AN INITIALIZATION PROCEDURE
App. No. 11/530,397
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DUTY CYCLE COUNTING PHASE CALIBRATION SCHEME OF AN INPUT/OUTPUT (I/O) INTERFACE
App. No. 11/516,382
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DIGITAL POWER-ON RESET
App. No. 11/511,783
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METHOD AND APPARATUS FOR FIXING BEST CASE HOLD TIME VIOLATIONS IN AN INTEGRATED CIRCUIT DESIGN
App. No. 11/509,370
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RANDOM SEED STABILITY WITH FUSES
App. No. 11/466,867
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SECURE, STABLE ON CHIP SILICON IDENTIFICATION
App. No. 11/466,885
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IDENTIFICATION CIRCUIT WITH REPEATABLE OUTPUT CODE
App. No. 11/466,876
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METHODS AND APPARATUS FOR IMPROVED RAID 1 MIRROR RE-SYNCHRONIZATION
App. No. 11/508,473
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CIRCUITS AND ASSOCIATED METHODS FOR IMPROVED DEBUG AND TEST OF AN APPLICATION INTEGRATED CIRCUIT
App. No. 11/508,585
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METHODS AND APPARATUS FOR IMPROVED ERROR AND ERASURE CORRECTION IN A REED-SOLOMON DATE CHANNEL
App. No. 11/507,156
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METHOD AND COMPUTER PROGRAM FOR STATIC TIMING ANALYSIS WITH DELAY DE-RATING AND CLOCK CONSERVATISM REDUCTION
App. No. 11/465,662
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INTEGRATED CIRCUIT PACKAGE AND SYSTEM INTERFACE
App. No. 11/506,680
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Method and system for creating and utilizing virtual hardware resources
App. No. 11/504,190
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ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CONTROL STRUCTURES IN RTL CODE
App. No. 11/460,680
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METHOD FOR REQUEST TRANSACTION ORDERING IN OCP BUS TO AXI BUS BRIDGE DESIGN
App. No. 11/490,691
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ARITHMETIC DECODE WITHOUT RENORMALIZATION COSTS
App. No. 11/483,056
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AUTOMATIC GENERATION OF TIMING CONSTRAINTS FOR THE VALIDATION/SIGNOFF OF TEST STRUCTURES
App. No. 11/478,044
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OPTIMIZING FOCUS POINT FOR OPTICAL DISC
App. No. 11/450,846
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STUB-TUNED WIREBOND PACKAGE
App. No. 11/437,059
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DIFFERENTIAL CURRENT-MODE DRIVER WITH HIGH COMMON-MODE RANGE AND CONTROLLED EDGE RATES
App. No. 11/413,497
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WAFER CHUCKING APPARATUS FOR SPIN PROCESSOR
App. No. 11/403,137
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SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMODATE HIGH SPEED CIRCUITRY GROUND ISOLATION
App. No. 11/399,723
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INTERDIGITATED MESH TO PROVIDE DISTRIBUTED, HIGH QUALITY FACTOR CAPACITIVE COUPLING
App. No. 11/397,252
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SYSTEM AND METHOD FOR DISPLAY COMPOSITING
App. No. 11/389,974
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DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
App. No. 11/277,188
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DEVICE FOR MINIMIZING DIFFERENTIAL PAIR LENGTH MISMATCH AND IMPEDANCE DISCONTINUITIES IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
App. No. 11/276,938
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VERIFICATION OF AN EXTRACTED TIMING MODEL FILE
App. No. 11/376,781
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APPARATUS AND METHODS FOR SIMPLIFIED SSP LINK LAYER PROCESSING
App. No. 11/374,260
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Apparatus and methods for a simplified, multi-client SAS port for management of other devices in an enhanced SAS device
App. No. 11/374,359
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SCALED COERCION OF DISK DRIVE CAPACITY
App. No. 11/366,921
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MULTI-BIT CONFIGURATION PINS
App. No. 11/366,735
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METHOD AND APPARATUS FOR INJECTING ERRORS INTO SAS DOMAINS THROUGH SAS EXPANDERS
App. No. 11/360,103
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APPARATUS AND METHODS FOR POWER MANAGEMENT AND SPIN-UP IN A STORAGE SYSTEM
App. No. 11/355,631
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PROGRESSIVE VIDEO DETECTION WITH AGGREGATED BLOCK SADS
App. No. 11/355,027
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GENERATION OF AN EXTRACTED TIMING MODEL FILE
App. No. 11/351,091
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CDM ESD EVENT SIMULATION AND REMEDIATION THEREOF IN APPLICATION CIRCUITS
App. No. 11/349,358
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CDM ESD EVENT PROTECTION IN APPLICATION CIRCUITS
App. No. 11/349,356
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ACTIVE CURRENT CANCELLATION FOR HIGH PERFORMANCE VIDEO CLAMPS
App. No. 11/345,929
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HYBRID MULTIPLE BIT-DEPTH VIDEO PROCESSING ARCHITECTURE
App. No. 11/325,291
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YIELD-LIMITING DESIGN-RULES-COMPLIANT PATTERN LIBRARY GENERATION AND LAYOUT INSPECTION
App. No. 11/323,468
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METHOD AND APPARATUS FOR DIVERTING VOID DIFFUSION IN INTEGRATED CIRCUIT CONDUCTORS
App. No. 11/323,398
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