Method and apparatus for fixing best case hold time violations in an integrated circuit design
View Patent ↗The disclosure is directed to a method and apparatus for fixing hold violations in an integrated circuit design. The method and apparatus trace upstream along a path in the design corresponding to the hold violation, from an end point of the path toward a start point of the path, until an element is reached that corresponds to the start point or has a fanout exceeding a predetermined fanout limit. The method and apparatus then generate an output that defines a location in the design at which to insert a delay element, such that the delay element is connected to an input of an element downstream of the element reached during tracing.
1. A method comprising:
(a) using an analysis tool, tracing upstream along a path within a design of an integrated circuit that corresponds to a hold violation, from an end point of the path toward a start point of the path, until an element is reached along the path that has a fanout exceeding a predetermined fanout limit; and
(b) generating an output that defines a location in the design at which to insert a delay element, the location being defined based on the element reached in (a).
2. The method of claim 1 , wherein the location defined in the output generated in step (b) is coupled to an input of an element along the path that is immediately downstream of the element reached in (a).
3. The method of claim 2 wherein the location is defined such that the delay element has an output that is connected only to the input of the downstream element.
4. The method of claim 1 wherein the output comprises a computer-readable engineering change order (ECO) file.
5. The method of claim 1 and further comprising:
(c) prior to step (a), inputting data from a timing report for the design and identifying the hold violation from the timing report.
6. The method of claim 5 and further comprising:
(d) repeating steps (a)-(c) for each of a plurality of hold violations identified from the timing report;
(e) inputting data from an updated timing report for the design from a static timing analysis tool, which has been updated to reflect the delay elements inserted in each iteration of step (b); and
f) further repeating steps (a)-(c) for each of a plurality of further hold violations identified from the updated timing report.
7. The method of claim 1 , wherein the start point and the end point comprise storage elements.
8. The method of claim 1 , wherein steps (a) and (b) are automated steps implemented through instructions executed by a computing device.
9. The method of claim 1 and further comprising:
c) selecting the delay element from a delay element table comprising a plurality of different delay element types, which have different delays, based on a magnitude of the hold violation.
10. The method of claim 9 wherein step (c) comprises:
(c) selecting the delay element from a delay element table comprising a plurality of different delay element types, which have different delays, based on a magnitude of the hold violation of the path and a magnitude of a setup time margin for that path.
11. ) The method of claim 9 and further comprising:
(d) prior to step (c), inputting a timing report for the design, generating the delay element table, inserting the plurality of different delay element types into the delay element table, and, for each different delay element type, assigning delay values to that delay element type based on a mathematical combination of delay values from the timing report for different instances of that delay element type that are included in the design.
12. The method of claim 1 , further comprising:
(c) terminating the tracing in step (a) when an element is reached along the path that corresponds to the start point and an element has not previously been reached along the path that has a fanout exceeding the predetermined fanout limit.
13. A computer-readable medium having computer-executable instructions that cause a computer to perform steps comprising:
(a) tracing upstream along a path within a design of an integrated circuit that corresponds to a hold violation, from an end point of the path toward a start point of the path, until an element is reached along the path that has a fanout exceeding a predetermined fanout limit; and
(b) generating an output that defines a location in the design at which to insert a delay element, the location being defined based on the element reached in (a).
14. The computer-readable medium of claim 13 wherein the location defined such that the delay element has an output that is coupled only to an element along the path that is immediately downstream of the element reached in (a).
15. The computer-readable medium of claim 13 further comprising:
(c) prior to step (a), inputting data from a timing report for the design and identifying the hold violation from the timing report.
16. The computer-readable medium of claim 15 further comprising:
(d) repeating steps (a)-(c) for each of a plurality of hold violations identified from the timing report;
(e) inputting data from an updated timing report for the design from a static timing analysis tool, which has been updated to reflect the delay elements inserted in each iteration of step (b); and
(f) further repeating steps (a)-(c) for each of a plurality of further hold violations identified from the updated timing report.
17. The computer-readable medium of claim 13 , wherein the start point and the end point comprise storage elements.
18. The computer-readable medium of claim 13 further comprising:
(c) selecting the delay element from a delay element table comprising a plurality of different delay element types, which have different delays, based on a magnitude of the hold violation.
19. The computer-readable medium of claim 18 wherein step (c) comprises:
(c) selecting the delay element from a delay element table comprising a plurality of different delay element types, which have different delays, based on a magnitude of the hold violation of the path and a magnitude of a setup time margin for that path.
20. The computer-readable medium of claim 18 further comprising:
(d) prior to step (c), inputting a timing report for the design, generating the delay element table, inserting the plurality of different delay element types into the delay element table, and, for each different delay element type, assigning delay values to that delay element type based on a mathematical combination of delay values from the timing report for different instances of that delay element type that are included in the design.
21. The computer-readable medium of claim 13 , wherein the steps further comprise:
(c) terminating the tracing in step (a) when an element is reached along the path that corresponds to the start point and an element has not previously been reached along the path that has a fanout exceeding the predetermined fanout limit.
22. An apparatus comprising:
a delay element table comprising a plurality of different delay element types and assigning a respective delay to each of the delay element types based on a mathematical combination of delay values from a timing report for different instances of that delay element type that are included in a design of an integrated circuit; and
a hold violation analysis tool, which is adapted to input data from a timing report for the design to identify a hold violation in the design, trace upstream along a path corresponding to the hold violation, from an end point of the path toward a start point of the path, until an element is reached along the path that corresponds to the start point or has a fanout exceeding a predetermined fanout limit, select a delay element from the plurality of different delay element types in the delay element table, and generate an output file that defines a location in the design at which to insert the delay element, such that the delay element is coupled to an input of an element along the path that is immediately downstream of the element reached along the path.