Patent Assignment
Reel/Frame 045216/0020
SECURITY INTEREST
Recorded: 2018-02-01
Received: 2018-02-01
Pages: 334
Assignors
BELL NORTHERN RESEARCH, LLC
Executed: 2018-01-24
BELL SEMICONDUCTOR, LLC
Executed: 2018-01-24
HILCO PATENT ACQUISITION 56, LLC
Executed: 2018-01-24
Assignee
CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
225 W. WASHINGTON ST., 9TH FLOOR, CHICAGO, IL, 60606, UNITED STATES
Covered Applications
(100)
STACKED INTERCONNECT HEAT SINK
App. No. 14/678,223
→
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
App. No. 14/305,794
→
INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS
App. No. 14/251,258
→
Method and Apparatus for Wide Bandwidth Mixed-Mode Wireless Communications
App. No. 14/094,107
→
Circuit Timing Analysis Incorporating the Effects of Temperature Inversion
App. No. 14/093,189
→
ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS
App. No. 14/073,526
→
Adaptive Infinite Impulse Response (IIR)-Based Code Detection for Symbol-Level Equalizer
App. No. 14/062,554
→
CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE
App. No. 14/057,441
→
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
App. No. 14/053,194
→
IQ IMBALANCE ESTIMATION USING BROADCAST SIGNALS
App. No. 14/050,922
→
ALTERNATE PAD STRUCTURES/PASSIVATION INTEGRATION SCHEMES TO REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES DURING CU/LOW-K BEOL PROCESSING
App. No. 14/045,081
→
INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
App. No. 14/010,842
→
HIERARCHICAL DESIGN FLOW GENERATOR
App. No. 13/971,560
→
Idle mode power consumption reduction in wireless communications
App. No. 13/947,182
→
CONTACT SUPPORT PILLAR STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE
App. No. 13/934,110
→
LOW POWER PROTOCOL FOR WIRELESS TERMINAL PEER-TO-PEER COMMUNICATIONS
App. No. 13/931,136
→
STACKED INTERCONNECT HEAT SINK
App. No. 13/921,707
→
PHOTOELECTRIC CONVERSION APPARATUS WITH GATE CONTROL LINES AND WIRING AT SAME HEIGHT
App. No. 13/871,742
→
METHOD AND SYSTEM FOR FRAME FORMATS FOR MIMO CHANNEL MEASUREMENT EXCHANGE
App. No. 13/856,708
→
CHANNEL TRAFFIC CONGESTION AVOIDANCE IN A MOBILE COMMUNICATION SYSTEM
App. No. 13/781,869
→
METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE
App. No. 13/775,922
→
OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
App. No. 13/761,828
→
SOLDER INTERCONNECT BY ADDITION OF COPPER
App. No. 13/752,524
→
FEEDBACK OF CHANNEL INFORMATION IN A CLOSED LOOP BEAMFORMING WIRELESS COMMUNICATION SYSTEM
App. No. 13/729,881
→
Maskless Vortex Phase Shift Optical Direct Write Lithography
App. No. 13/722,648
→
Enhanced Higher Priority Public Land Mobile Network (HPPLMN) Search
App. No. 13/706,009
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IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
App. No. 13/681,283
→
METHOD OF MANUFACTURING AN ELECTRONIC DEVICE PACKAGE
App. No. 13/677,547
→
Staged Scenario Generation
App. No. 13/658,336
→
METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER
App. No. 13/657,000
→
ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER
App. No. 13/656,092
→
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
App. No. 13/649,996
→
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
App. No. 13/649,909
→
CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE
App. No. 13/627,054
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SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
App. No. 13/599,549
→
METHOD AND SYSTEM FOR INTERFERENCE SUPPRESSION IN WCDMA SYSTEMS
App. No. 13/588,297
→
SOLDERING METHOD AND RELATED DEVICE FOR IMPROVED RESISTANCE TO BRITTLE FRACTURE
App. No. 13/552,266
→
Characterizing Performance of an Electronic System
App. No. 13/549,599
→
METHOD AND APPARATUS FOR GENERATING MEMORY MODELS AND TIMING DATABASE
App. No. 13/547,884
→
A METHOD AND COMPUTER PROGRAM FOR GENERATING GROUNDED SHIELDING WIRES FOR SIGNAL WIRING
App. No. 13/544,632
→
LOW POWER PROTOCOL FOR WIRELESS TERMINAL PEER-TO-PEER COMMUNICATIONS
App. No. 13/534,538
→
Methods and Systems for Pre-Emphasis of an Envelope Tracking Power Amplifier Supply Voltage
App. No. 13/492,279
→
METHOD AND APPARATUS FOR DUAL FREQUENCY TIMING ACQUISITION FOR COMPRESSED WCDMA COMMUNICATION NETWORKS
App. No. 13/489,169
→
Cordless Telephone With Digital Audio Player Capability
App. No. 13/472,780
→
SYSTEM AND METHOD FOR CONSERVING BATTERY POWER IN A MOBILE STATION
App. No. 13/472,940
→
MULTI-PASS ROUTING TO REDUCE CROSSTALK
App. No. 13/467,696
→
CIRCUIT TIMING ANALYSIS INCORPORATING THE EFFECTS OF TEMPERATURE INVERSION
App. No. 13/453,289
→
INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
App. No. 13/443,691
→
AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE
App. No. 13/442,099
→
METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME
App. No. 13/428,540
→
Methods and Systems for Pre-Emphasis of an Envelope Tracking Power Amplifier Supply Voltage
App. No. 61/611,718
→
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
App. No. 13/421,710
→
Method and Apparatus for Channel Traffic Congestion Avoidance in a Mobile Communication System
App. No. 13/418,967
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LOW DEPTH CIRCUIT DESIGN
App. No. 13/407,830
→
PORTABLE CELL PHONE AND A PROIMITY REGULATION SYSTEM FOR USE WITH A PORTABLE CELL PHONE
App. No. 13/398,656
→
CIRCUITS AND METHODS FOR IMPROVED FET MATCHING
App. No. 13/368,985
→
SYSTEM AND METHOD FOR MANAGING TIMING MARGIN IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
App. No. 13/367,094
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BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR
App. No. 13/348,415
→
ALUMINUM BOND PADS WITH ENHANCED WIRE BOND STABILITY
App. No. 13/344,207
→
SEMICONDUCTOR DEVICE AND PROCESS FOR REDUCING DAMAGING BREAKDOWN IN GATE DIELECTRICS
App. No. 13/311,299
→
LOCATION-BASED SEARCH-RESULT RANKING FOR BLOG DOCUMENTS AND THE LIKE
App. No. 13/292,170
→
MASKLESS VORTEX PHASE SHIFT OPTICAL DIRECT WRITE LITHOGRAPHY
App. No. 13/253,554
→
METHODS FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
App. No. 13/252,632
→
TIMING SIGNOFF SYSTEM AND METHOD THAT TAKES STATIC AND DYNAMIC VOLTAGE DROP INTO ACCOUNT
App. No. 13/246,102
→
BIPOLAR DEVICE HAVING BURIED CONTACTS
App. No. 13/222,877
→
LOW-COST 3D FACE-TO-FACE OUT ASSEMBLY
App. No. 13/217,857
→
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
App. No. 13/212,427
→
BACKWARD-COMPATIBLE LONG TRAINING SEQUENCES FOR WIRELESS COMMUNICATION NETWORKS
App. No. 13/196,082
→
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
App. No. 13/174,970
→
METHOD AND APPARATUS FOR BALANCING SIGNAL DELAY SKEW
App. No. 13/173,855
→
STAGED SCENARIO GENERATION
App. No. 13/150,607
→
HIGH VOLTAGE TOLERANT METAL-OXIDE-SEMICONDUCTOR DEVICE
App. No. 13/149,122
→
FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY
App. No. 13/114,834
→
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 13/110,581
→
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
App. No. 13/103,461
→
METHOD AND SYSTEM FOR FRAME FORMATS FOR MIMO CHANNEL MEASUREMENT EXCHANGE
App. No. 13/100,014
→
INTELLIGENT DUMMY METAL FILL PROCESS FOR INTEGRATED CIRCUITS
App. No. 13/099,948
→
CORDLESS TELEPHONE WITH DIGITAL AUDIO PLAYER CAPABILITY
App. No. 13/096,420
→
SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE
App. No. 13/093,032
→
METHOD AND APPARATUS FOR WIDE BANDWIDTH MIXED-MODE WIRELESS COMMUNICATIONS
App. No. 13/069,108
→
ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS
App. No. 13/119,005
→
LOGIC-BASED EDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS
App. No. 13/046,973
→
CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
App. No. 13/041,674
→
DECOUPLING CAPACITOR
App. No. 13/032,429
→
Method and Apparatus for Channel Traffic Congestion Avoidance in a Mobile Communication System
App. No. 13/031,355
→
MITIGATION OF WHISKERS IN SN-FILMS
App. No. 13/059,502
→
Prioritizing RACH Message Contents
App. No. 13/026,512
→
MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
App. No. 13/026,528
→
SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUITS THAT EMPLOY ADAPTIVE VOLTAGE SCALING OPTIMIZATION
App. No. 13/058,176
→
METHOD OF FABRICATION OF THROUGH-SUBSTRATE VIAS
App. No. 12/969,836
→
INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS
App. No. 12/969,852
→
MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK
App. No. 12/953,624
→
INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
App. No. 12/947,948
→
EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A NANOTUBE STRUCTURE
App. No. 12/912,791
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NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
App. No. 12/905,301
→
METHODS AND SYSTEMS FOR PERFORMING TIMING SIGN-OFF OF AN INTEGRATED CIRCUIT DESIGN
App. No. 12/901,588
→
Digitally Obtaining Contours of Fabricated Polygons
App. No. 12/890,336
→
HYBRID BUMP CAPACITOR
App. No. 12/885,722
→
Low Cost 3D-Face to Face Fan Out F2FFO Assembly
App. No. 61/377,171
→
GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION
App. No. 12/840,535
→