Granted Patent B2

US 8,572,543 · App. 13/442,099 · Granted Oct 29, 2013

Abstract

Claims (43)

1. A method of designing an integrated circuit, comprising the steps of:

(A) generating a design layout of said integrated circuit in a computer, said design layout comprising (i) a plurality of common cells each configured to perform a logical operation and (ii) a logic gate having a logic input fixed to a logic level;

(B) replacing at least one of said common cells proximate said logic gate with a special cell configured to (i) perform said logical operation and (ii) generate a signal at said logic level;

(C) removing a connection that fixes said logic input of said logic gate to said logic level;

(D) routing said signal from said special cell to said logic input of said logic gate, wherein (i) said logic gate resides inside a first of a plurality of boundaries in said design layout, (ii) said design layout further comprises a scan chain having a scan cell within said first boundary, (iii) an additional logic gate resides in a second of said boundaries and (iv) said second boundary adjoins said first boundary; and

(E) marking said second boundary as full in response to said second boundary lacking available space to place another scan cell.

2. The method according to claim 1 , wherein said logical operation comprises a flip-flop operation.

3. The method according to claim 1 , wherein said special cell is configured to generate said signal at a logical high level.

4. The method according to claim 1 , wherein said special cell is configured to generate said signal at a logical low level.

5. The method according to claim 1 , wherein said design layout further comprises another logic gate having another logic input fixed to said logic level, the method further comprising the steps of:

removing another connection that fixes said other logic input of said other logic gate to said logic level; and

routing said signal from said special cell to said other logic input of said other logic gate.

6. The method according to claim 1 , wherein said design layout further comprises another logic gate having another logic input fixed to said logic level, the method further comprising the steps of:

adding a tie-to cell to said design layout proximate said other logic gate, wherein said tie-to cell is configured to generate another signal at said logic level;

removing another connection that fixes said other logic input of said other logic gate to said logic level; and

routing said other signal from said tie-to cell to said other logic input of said other logic gate.

7. The method according to claim 1 , wherein (i) said special cell comprises a given scan cell and (ii) said design layout further comprises another logic gate having another logic input fixed to a particular logic level.

8. The method according to claim 7 , further comprising the steps of:

removing another connection that fixes said other logic input of said other logic gate to said particular logic level; and

routing a data output of said given scan cell to said other logic input of said other logic gate.

9. The method according to claim 7 , further comprising the step of:

routing a data output of said given scan cell to another scan cell in said design layout.

10. The method according to claim 1 , further comprising the steps of:

rerouting said logic input of said logic gate to a data output of said scan cell.

11. The method according to claim 1 , wherein the steps are preformed by processor executable instructions contained within a non-transitory computer readable medium.

12. A method of designing an integrated circuit, comprising the steps of:

(A) generating a design layout of said integrated circuit in a computer, said design layout comprising (i) a scan chain and (ii) a plurality of logic gates, at least one of said logic gates having a logic input fixed to a logic level and residing inside a first of a plurality of boundaries in said design layout;

(B) adding a scan cell within said first boundary;

(C) rerouting said logic input of said at least one logic gate to a data output of said scan cell; and

(D) rerouting said scan chain to include said scan cell.

13. The method according to claim 12 , wherein (i) another of said logic gates resides in a second of said boundaries and (ii) said second boundary adjoins said first boundary, the method further comprising the step of:

marking said second boundary as full in response to said second boundary lacking available space to place another scan cell.

14. The method according to claim 12 , further comprising the step of:

adding another scan cell within said first boundary in response to a second boundary being marked as full.

15. The method according to claim 14 , further comprising the step of:

rerouting another logic input of another cell in said second boundary to a data output of said other scan cell.

16. The method according to claim 12 , wherein said design layout further comprises (i) a plurality of common cells each configured to perform a logical operation and (ii) another of said logic gates having another logic input fixed to said logic level.

17. The method according to claim 16 , further comprising the steps of:

replacing at least one of said common cells proximate said other logic gate with a special cell configured to (i) perform said logical operation and (ii) generate a signal at said logic level;

removing a connection that fixes said other logic input of said other logic gate to said logic level; and

routing said signal from said special cell to said other logic input of said other logic gate.

18. The method according to claim 16 , wherein said logical operation comprises a flip-flop operation.

19. The method according to claim 12 , wherein the steps are preformed by processor executable instructions contained within a non-transitory computer readable medium.

Assignments (8)