Patent Assignment
Reel/Frame 044887/0109
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2017-12-17
Received: 2017-12-17
Pages: 80
Assignors
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Executed: 2017-12-08
BROADCOM CORPORATION
Executed: 2017-12-08
Assignee
BELL SEMICONDUCTOR, LLC
401 N. MICHIGAN AVE., SUITE 1600, CHICAGO, IL, 60611, UNITED STATES
Covered Applications
(100)
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
App. No. 14/305,794
→
Circuit Timing Analysis Incorporating the Effects of Temperature Inversion
App. No. 14/093,189
→
CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE
App. No. 14/057,441
→
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
App. No. 14/053,194
→
INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
App. No. 14/010,842
→
HIERARCHICAL DESIGN FLOW GENERATOR
App. No. 13/971,560
→
OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
App. No. 13/761,828
→
IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
App. No. 13/681,283
→
Staged Scenario Generation
App. No. 13/658,336
→
METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER
App. No. 13/657,000
→
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
App. No. 13/649,996
→
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
App. No. 13/649,909
→
CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE
App. No. 13/627,054
→
SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
App. No. 13/599,549
→
Characterizing Performance of an Electronic System
App. No. 13/549,599
→
METHOD AND APPARATUS FOR GENERATING MEMORY MODELS AND TIMING DATABASE
App. No. 13/547,884
→
A METHOD AND COMPUTER PROGRAM FOR GENERATING GROUNDED SHIELDING WIRES FOR SIGNAL WIRING
App. No. 13/544,632
→
MULTI-PASS ROUTING TO REDUCE CROSSTALK
App. No. 13/467,696
→
CIRCUIT TIMING ANALYSIS INCORPORATING THE EFFECTS OF TEMPERATURE INVERSION
App. No. 13/453,289
→
AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE
App. No. 13/442,099
→
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
App. No. 13/421,710
→
LOW DEPTH CIRCUIT DESIGN
App. No. 13/407,830
→
SYSTEM AND METHOD FOR MANAGING TIMING MARGIN IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
App. No. 13/367,094
→
TIMING SIGNOFF SYSTEM AND METHOD THAT TAKES STATIC AND DYNAMIC VOLTAGE DROP INTO ACCOUNT
App. No. 13/246,102
→
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
App. No. 13/212,427
→
METHOD AND APPARATUS FOR BALANCING SIGNAL DELAY SKEW
App. No. 13/173,855
→
STAGED SCENARIO GENERATION
App. No. 13/150,607
→
FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY
App. No. 13/114,834
→
TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT
App. No. 13/103,461
→
INTELLIGENT DUMMY METAL FILL PROCESS FOR INTEGRATED CIRCUITS
App. No. 13/099,948
→
SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUITS THAT EMPLOY ADAPTIVE VOLTAGE SCALING OPTIMIZATION
App. No. 13/058,176
→
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
App. No. 12/905,301
→
METHODS AND SYSTEMS FOR PERFORMING TIMING SIGN-OFF OF AN INTEGRATED CIRCUIT DESIGN
App. No. 12/901,588
→
Digitally Obtaining Contours of Fabricated Polygons
App. No. 12/890,336
→
GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION
App. No. 12/840,535
→
IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
App. No. 12/836,274
→
METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER
App. No. 12/791,260
→
TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
App. No. 12/779,312
→
GENERATION OF AN EXTRACTED TIMING MODEL FILE
App. No. 12/695,396
→
SPECIAL ENGINEERING CHANGE ORDER CELLS
App. No. 12/608,469
→
BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING THE SAME
App. No. 12/576,775
→
ESTABLISHING BENCHMARKS FOR ANALYZING BENEFITS ASSOCIATED WITH VOLTAGE SCALING, ANALYZING THE BENEFITS AND AN APPARATUS THEREFOR
App. No. 12/510,082
→
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
App. No. 12/510,104
→
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS
App. No. 12/510,122
→
GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS
App. No. 12/508,898
→
METHOD AND APPARATUS FOR GENERATING MEMORY MODELS AND TIMING DATABASE
App. No. 12/508,320
→
AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE
App. No. 12/463,509
→
I/O PLANNING WITH LOCK AND INSERTION FEATURES
App. No. 12/432,996
→
SYSTEM AND METHOD FOR CLOCK OPTIMIZATION TO ACHIEVE TIMING SIGNOFF IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME
App. No. 12/423,001
→
METHOD AND AN APPARATUS FOR EVALUATING SMALL DELAY DEFECT COVERAGE OF A TEST PATTERN SET ON AN IC
App. No. 12/421,481
→
AUTOMATED TIMING OPTIMIZATION
App. No. 12/421,198
→
INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI
App. No. 12/388,741
→
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS
App. No. 12/365,084
→
SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
App. No. 12/365,010
→
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
App. No. 12/364,918
→
ARCHITECTURALLY INDEPENDENT NOISE SENSITIVITY ANALYSIS OF INTEGRATED CIRCUITS HAVING A MEMORY STORAGE DEVICE AND A NOISE SENSITIVITY ANALYZER
App. No. 12/347,916
→
MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEM
App. No. 12/340,234
→
METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS
App. No. 12/336,472
→
DECODER USING A MEMORY FOR STORING STATE METRICS IMPLEMENTING A DECODER TRELLIS
App. No. 12/336,104
→
METHOD AND SYSTEM FOR OUTPUTTING A SEQUENCE OF COMMANDS AND DATA DESCRIBED BY A FLOWCHART
App. No. 12/315,998
→
REDUCING PATH DELAY SENSITIVITY TO TEMPERATURE VARIATION IN TIMING-CRITICAL PATHS
App. No. 12/251,110
→
CIRCUIT TIMING ANALYSIS INCORPORATING THE EFFECTS OF TEMPERATURE INVERSION
App. No. 12/251,088
→
LOW DEPTH CIRCUIT DESIGN
App. No. 12/248,187
→
CHANNEL LENGTH SCALING FOR FOOTPRINT COMPATIBLE DIGITAL LIBRARY CELL DESIGN
App. No. 12/248,677
→
CRITICAL PATH MONITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
App. No. 12/247,992
→
ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLACEMENT OF PROCESS MONITORS IN AN INTEGRATED CIRCUIT
App. No. 12/248,016
→
CONTROL SIGNAL SOURCE REPLICATION
App. No. 12/243,768
→
DESIGN OPTIMIZATION WITH ADAPTIVE BODY BIASING
App. No. 12/240,210
→
AUTOMATED SPECIFICATION BASED FUNCTIONAL TEST GENERATION INFRASTRUCTURE
App. No. 12/212,736
→
WAIVER MECHANISM FOR PHYSICAL VERIFICATION OF SYSTEM DESIGNS
App. No. 12/211,238
→
DUAL PATH STATIC TIMING ANALYSIS
App. No. 12/206,048
→
VIRTUAL DATA REPRESENTATION THROUGH SELECTIVE BIDIRECTIONAL TRANSLATION
App. No. 12/201,575
→
DISABLING UNUSED IO RESOURCES IN PLATFORM-BASED INTEGRATED CIRCUITS
App. No. 12/229,446
→
SYNTHESIZED LOGIC REPLACEMENT
App. No. 12/193,566
→
SYSTEM AND METHOD FOR REDUCING THE GENERATION OF INCONSEQUENTIAL VIOLATIONS RESULTING FROM TIMING ANALYSES
App. No. 12/190,784
→
Methods for Measurement and Prediction of Hold-Time and Exceeding Hold Time Limits Due to Cells with Tied Input Pins
App. No. 12/187,464
→
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT
App. No. 12/186,159
→
ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR EMPLOYING UNSENSITIZED CRITICAL PATH INFORMATION TO REDUCE LEAKAGE POWER IN AN INTEGRATED CIRCUIT
App. No. 12/182,330
→
METHOD FOR ESTIMATION OF TRACE INFORMATION BANDWIDTH REQUIREMENTS
App. No. 12/144,248
→
LANGUAGE AND TEMPLATES FOR USE IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
App. No. 12/122,307
→
RULES AND DIRECTIVES FOR VALIDATING CORRECT DATA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
App. No. 12/120,965
→
CHARACTERIZING PERFORMANCE OF AN ELECTRONIC SYSTEM
App. No. 12/120,894
→
METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT DESIGN FOR STATIC TIMING ANALYSIS
App. No. 12/117,760
→
OPTIMIZING TEST CODE GENERATION FOR VERIFICATION ENVIRONMENT
App. No. 12/117,381
→
ACCURATE PIN-BASED MEMORY POWER MODEL USING ARC-BASED CHARACTERIZATION
App. No. 12/150,846
→
OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
App. No. 12/111,836
→
UNIFIED LAYER STACK ARCHITECTURE
App. No. 12/109,501
→
ON CHIP LOCAL MOSFET SIZING
App. No. 12/103,825
→
PROBABILISTIC NOISE ANALYSIS
App. No. 12/046,169
→
Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow
App. No. 12/072,478
→
SIGNAL DELAY SKEW REDUCTION SYSTEM
App. No. 12/015,925
→
STAGED SCENARIO GENERATION
App. No. 11/949,187
→
TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL
App. No. 11/946,243
→
AUTOMATED SPECIFICATION BASED FUNCTIONAL TEST GENERATION INFRASTRUCTURE
App. No. 60/973,550
→
STATISTICAL DESIGN CLOSURE
App. No. 11/849,391
→
NQL - NETLIST QUERY LANGUAGE
App. No. 11/832,516
→
GENERALIZED BIST FOR MULTIPORT MEMORIES
App. No. 11/775,956
→
EFFICIENT CELL SWAPPING SYSTEM FOR LEAKAGE POWER REDUCTION IN A MULTI-THRESHOLD VOLTAGE PROCESS
App. No. 11/765,691
→
DIGITAL GAUSSIAN NOISE SIMULATOR
App. No. 11/758,975
→
RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES
App. No. 11/757,229
→