Low depth circuit design
A method of designing a logic circuit based on one of the functions of the form f n =x 1 (x 2 & (x 3 (x 4 & . . . x n . . . ))) and f′ n =x 1 & (x 2 (x 3 & (x 4 . . . x n . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.
1. A processor-based method of designing a logic circuit based on one of the functions of the form:
f n =x 1 ( x 2 & ( x 3 ( x 4 & . . . x n . . . ))), and
f′ n =x 1 & ( x 2 ( x 3 & ( x 4 . . . x n . . . ))),
comprising the steps of:
a. selecting N as the number of variables of the logic circuit,
b. testing N against a threshold,
c. for values of N less than the threshold, using a first algorithm to design the logic circuit using the processor, where the first algorithm is a heuristic optimization of a base algorithm; adapted for reduced accuracy and enhanced speed of computation, and
d. for values of N greater than the threshold, using a second algorithm to design the logic circuit using the processor, where
the second algorithm is an n-restricted algorithm that uses, in all arrays of the base algorithm, only elements that have n-good binary expansions,
loops of the base algorithm having a form of for(i=0; i<NN; i++) are replaced with for(i=0; i<NN; i=next after i number with n-good expansion),
conditions of the base algorithm having a form of if(depth[k]>d) are replaced with if(k is n-good) if(depth[k]>d), and
the second algorithm operates with the logic circuits such that passports of all subfunctions are n-good, and
e. the base algorithm is characterized by a search of all possible combinations of the logic circuit, and a selection of the logic circuit having a lowest depth.
2. The method of claim 1 , wherein n equals four.
3. The method of claim 1 , wherein the logic circuit comprises data paths including at least one of binary adders, binary comparators, and locators of leading and trailing ones and zeros in binary numbers.
4. The method of claim 1 , wherein the first algorithm is a modification of the base algorithm, where traces for any given depth D and for a given b are only kept to a value of c=c(b,D) that is maximum among all c such that functions with passport (0,b,c,N+1−b−c) have a depth that is not more than D.
5. The method of claim 1 , wherein the base algorithm comprises selecting a preexisting design having the least number of variables that is greater than N, and simplifying the preexisting design for N variables by setting constants to unused inputs and applying constant propagation.
6. The method of claim 1 , wherein the threshold is about 698.
7. A processor-based method of designing a logic circuit based on one of the functions of the form:
f n =x 1 ( x 2 & ( x 3 ( x 4 & . . . x n . . . ))), and
f′ n =x 1 & ( x 2 ( x 3 & ( x 4 . . . x n . . . ))),
comprising the steps of:
a. selecting N as the number of variables of the logic circuit,
b. testing N against a first threshold,
c. for values of N less than the threshold, using a first algorithm to design the logic circuit using the processor, where the first algorithm is one of,
i. a modification of a base algorithm that uses only elements that have n-good binary expansions, where:
loops of the base algorithm having a form of for(i=0; i<NN; i++) are replaced with for(i=0; i<NN; i=next after i number with n-good expansion),
conditions of the base algorithm having a form of if(depth[k]>d) are replaced with if(k is n-good) if(depth[k]>d), and
the second algorithm operates with the logic circuits such that passports of all subfunctions are n-good, and
ii. a modification of the base algorithm, where traces for any given depth D and for a given b are only kept to a value of c=c(b,D) that is maximum among all c such that functions with passport (0,b,c,N+1−b−c) have a depth that is not more than D, and
d. the base algorithm is characterized by a search of all possible combinations of the logic circuit, and a selection of the logic circuit having a lowest depth.
8. The method of claim 7 , wherein the threshold is about 698.
9. The method of claim 7 , wherein n equals four.
10. The method of claim 7 , wherein the logic circuit comprises data paths including at least one of binary adders, binary comparators, and locators of leading and trailing ones and zeros in binary numbers.
11. The method of claim 7 , wherein the base algorithm comprises selecting a preexisting design having the least number of variables that is greater than N, and simplifying the preexisting design for N variables by setting constants to unused inputs and applying constant propagation.