Methods for designing integrated circuits employing context-sensitive and progressive rules and an apparatus employing one of the methods
View Patent ↗Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.
1. A method of designing an integrated circuit employing a hierarchical design flow, comprising:
(a) creating a functional circuit for a functional block of an IC design;
(b) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said hierarchical design flow;
(c) synthesizing a logical circuit based on said functional circuit;
(d) verifying said logical circuit satisfies said rule-set;
(e) implementing a physical layout of said logical circuit; and
(f) verifying said physical layout satisfies said rule-set, wherein each step of said method is carried out by at least one EDA tool.
2. The method as recited in claim 1 wherein said steps a-f are performed for multiple functional blocks of said IC design.
3. The method as recited in claim 2 wherein at least some of said steps a-f are performed in parallel.
4. The method as recited in claim 1 wherein said hierarchical design flow includes a functional context, a logical context and a physical context.
5. The method as recited in claim 1 wherein said rule-set is configured to facilitate convergence of said IC design.
6. The method as recited in claim 1 wherein at least one rule of said rule-set includes multiple requirements that are context-based.
7. The method as recited in claim 1 wherein each rule of said rule-set is directed to a compliance requirement for said IC design.
8. The method as recited in claim 7 wherein said rule-set includes different categories of rules selected from the group consisting of:
clock/reset rules,
connectivity rules
timing rules, and
physical rules.
9. The method as recited in claim 1 wherein said rule-set includes information guidelines for said IC design.
10. The method as recited in claim 1 wherein at least some rules of said rule-set include a greater number of compliance requirements as said hierarchical design flow matures.
11. A method of designing an integrated circuit, comprising:
employing at least a first EDA tool to create a functional circuit of an IC design, synthesize a logical circuit based on said functional circuit and implement a physical layout of said logical circuit;
employing at least a second EDA tool for verifying that each of said functional circuit, said logical circuit and said physical layout satisfies a rule-set for said IC design, wherein said rule-set is context-based and progressive;
modifying said functional circuit, said logical circuit or said physical layout if needed according to said verifying.
12. The method as recited in claim 11 wherein said rule-set has a maximum of twenty rules.
13. The method as recited in claim 11 wherein at least one rule of said rule-set includes at least one requirement that is context-based.
14. The method as recited in claim 11 wherein said rule-set includes different categories of rules selected from the group consisting of:
clock/reset rules,
connectivity rules,
timing rules and
physical rules.
15. The method as recited in claim 11 wherein said rule-set includes rules designed to facilitate convergence of said IC design.
16. An apparatus, comprising:
an analyzer configured to compare a context stage of a hierarchical design flow of an IC design with a rule-set of said IC design; and
a verifier configured to determine compliance of said context stage with said rule-set, wherein said rule-set is context-based.
17. The apparatus as recited in claim 16 wherein said rule-set includes different categories of rules selected from the group consisting of:
clock/reset rules, and
connectivity rules.
18. The apparatus as recited in claim 16 wherein said verifier is configured to adjust determining compliance with said rule-set based on a maturity of said IC design.
19. The apparatus as recited in claim 16 wherein said rule-set includes different categories of rules selected from the group consisting of:
timing rules and
physical rules.
20. The apparatus as recited in claim 16 wherein said rule-set is applicable for each functional block of said hierarchical design flow.