Granted Patent B2

US 8,112,734 · App. 12/240,210 · Granted Feb 7, 2012

Abstract

Claims (42)

1. A method incorporating adaptive body biasing into an integrated circuit design flow comprising the steps of:

providing a cell library for said integrated circuit design flow, wherein said cell library is stored in a non-transitory computer readable medium and specifies a plurality of adaptive body biasing corners, each adaptive body biasing corner defining respective process, voltage, temperature, and body biasing voltage parameters;

adding adaptive body biasing input/outputs (I/Os) to a layout of an integrated circuit design to implement said adaptive body biasing, wherein said adaptive body biasing I/Os are added during a bonding layout stage of said integrated circuit design flow;

performing a floorplanning operation that includes adding at least one bias voltage source to the integrated circuit design layout by using a computer;

performing an adaptive body biasing mesh layout operation; and

performing a place and route operation configured to retrieve and utilize at least one of said plurality of adaptive body biasing corners from said cell library.

2. The method according to claim 1 , further comprising the step of:

performing mesh analysis on the integrated circuit design layout.

3. The method according to claim 2 , further comprising the step of:

performing a static timing analysis on the integrated circuit design layout, wherein said static timing analysis is configured to retrieve at least one of (i) adaptive body biasing optimization corners from said cell library and (ii) static timing analysis scripts configured to take into account the adaptive body biasing optimization corners from said cell library.

4. The method according to claim 3 , further comprising the step of:

performing board level analysis of said layout of said integrated circuit design.

5. The method according to claim 3 , further comprising the step of:

performing a design rule check (DRC) and layout versus schematic (LVS) analysis that includes checking for a deep N-well addition in the integrated circuit design layout.

6. The method according to claim 1 , further comprising the step of performing board level planning prior to said bonding layout stage.

7. The method according to claim 1 , wherein the step of generating said layout of said integrated circuit design is further based upon adaptive voltage scaling (AVS) corners.

8. The method according to claim 1 , wherein the plurality of adaptive body biasing corners comprise maximum, nominal and minimum values for a body biasing voltage.

9. The method according to claim 1 , wherein the plurality of adaptive body biasing corners comprise at least two values in addition to maximum, nominal and minimum values for a body biasing voltage.

10. A computer system incorporating adaptive body biasing optimization during design closure of an integrated circuit design, said computer system configured to:

add adaptive body biasing input/outputs (I/Os) to a layout of an integrated circuit design to implement said adaptive body biasing, wherein said adaptive body biasing I/Os are added during a bonding layout stage of an integrated circuit design flow;

perform a floorplanning operation that includes adding at least one bias voltage source to the layout for said integrated circuit design by using a computer;

perform an adaptive body biasing mesh layout operation for said integrated circuit design; and

perform a place and route operation configured to retrieve and utilize at least one of a plurality of adaptive body biasing optimization corners, wherein said plurality of adaptive body biasing optimization corners are retrieved from a cell library and define process, voltage, temperature, and body biasing voltage parameters for respective cells of said cell library.

11. The computer system according to claim 10 , further comprising a routine configured to:

perform mesh analysis on the layout of said integrated circuit design.

12. The computer system according to claim 11 , further comprising a routine configured to:

perform a static timing analysis on the integrated circuit design layout, wherein said static timing analysis is configured to retrieve at least one of (i) adaptive body biasing optimization corners from said cell library and (ii) static timing analysis scripts configured to take into account the adaptive body biasing optimization corners from said cell library.

13. The computer system according to claim 12 , further comprising a routine configured to

perform board level analysis of said layout of said integrated circuit design.

14. The computer system according to claim 12 , further comprising a routine configured to:

perform a design rule check (DRC) and layout versus schematic (LVS) analysis that includes checking for a deep N-well addition to the integrated circuit design layout.

15. The computer system according to claim 10 , further comprising a routine configured to perform board level planning prior to said bonding layout stage.

16. The computer system according to claim 10 , wherein the generation of said layout of said integrated circuit design is further based upon adaptive voltage scaling (AVS) corners.

17. The computer system according to claim 10 , wherein the plurality of adaptive body biasing corners comprise maximum, nominal and minimum values for a body biasing voltage.

18. The computer system according to claim 10 , wherein the plurality of adaptive body biasing corners comprise at least two values in addition to maximum, nominal and minimum values for a body biasing voltage.

19. A non-transitory computer readable medium, which when executed by a computer incorporates adaptive body biasing into an integrated circuit design flow, comprising the steps of:

adding adaptive body biasing input/outputs (I/Os) to a layout of an integrated circuit design to implement said adaptive body biasing, wherein said adaptive body biasing I/Os are added during a bonding layout stage of said integrated circuit design flow;

performing a floorplanning operation that includes adding at least one bias voltage source to the integrated circuit design layout by using a computer;

performing an adaptive body biasing mesh layout operation; and

performing a place and route operation configured to retrieve and utilize at least one of a plurality of adaptive body biasing corners from a cell library, wherein said cell library is stored in said non-transitory computer readable medium and specifies a plurality of adaptive body biasing corners, each adaptive body biasing corner defining respective process, voltage, temperature, and body biasing voltage parameters.

20. The non-transitory computer readable medium according to claim 19 , wherein said cell library further comprises:

information characterizing a plurality of adaptive voltage scaling corners for said plurality of cells.

Assignments (9)