Ramptime propagation on designs with cycles
View Patent ↗A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.
1. A ramptime evaluation tool adapted to calculate ramptime values for pins in an oriented graph based on an integrated circuit layout design, the ramptime evaluation tool adapted to localize cycled parts of the integrated circuit layout design and to calculate iteratively only those ramptime values associated with pins in the cycled parts of the integrated circuit layout design.
2. The ramptime evaluation tool of claim 1 wherein the ramptime evaluation tool calculates ramptimes for all pins not associated with pins in the localized cycled parts of the integrated circuit layout design using a level assignment algorithm adapted to calculate a ramptime based on predefined ramptimes of other pins in the integrated circuit layout design.
3. The ramptime evaluation tool of claim 2 wherein the level assignment algorithm assigns each pin of the integrated circuit layout design to a level of a plurality of levels according to inputs associated with the pin.
4. The ramptime evaluation tool of claim 3 wherein ramptimes for pins assigned to a particular level are calculated in parallel.
5. The ramptime evaluation tool of claim 1 wherein the ramptime evaluation tool is adapted to integrate ramptime calculations from the localized cycled parts of the integrated circuit layout design into a level assignment algorithm.