CIRCUITS AND METHODS FOR EFFICIENT CLOCK AND DATA DELAY CONFIGURATION FOR FASTER TIMING CLOSURE
Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps.
1 . An integrated circuit, comprising:
a first macro circuit block having an input;
a second macro circuit block having an input;
a first configurable delay circuit having an output connected to the input of the first macro circuit block;
a second configurable delay circuit having an output connected to the input of the second macro circuit block; and
a signal distribution network having an output connected to an input of the first configurable delay circuit;
wherein the first configurable delay circuit and the second configurable delay circuit have a same footprint, but have different delay characteristics.
2 . The integrated circuit of claim 1 , wherein the output of the signal distribution network is connected to an input of the second configurable delay circuit.
3 . The integrated circuit of claim 1 , wherein the signal distribution network is a clock signal distribution network, and wherein the input of the first macro circuit block is a clock input.
4 . The integrated circuit of claim 1 , wherein the signal distribution network is a data signal distribution network, and wherein the input of the first macro circuit block is a data input.
5 . The integrated circuit of claim 1 , wherein the first and second configurable delay circuits each comprise a chain of buffers, wherein a number of buffers in the chain of buffers is the same in the first and second configurable delay circuits.
6 . The integrated circuit of claim 5 , wherein a total delay for a given one of the first and second configurable delay circuits is based on a number of buffers in the chain of buffers, which are serially connected between an input and output of the given configurable delay circuit.
7 . The integrated circuit of claim 1 , further comprising a third configurable delay circuit having footprint that is different than the footprints of the first and second configurable delay circuits.
8 . The integrated circuit of claim 7 , further comprising a third macro circuit block having an input connected to an output of the third configurable delay circuit.
9 . The integrated circuit of claim 7 , wherein an output of the third configurable delay circuit is connected to an input of the second configurable delay circuit.
10 . The integrated circuit of claim 9 , wherein an input of the third configurable delay circuit is connected to an output of the signal distribution network.
11 . A chip package comprising the integrated circuit of claim 1 .
12 . An integrated circuit, comprising:
a macro circuit block having an input;
a signal distribution network having an output; and
a chain of configurable delay circuits serially connected between the input of the macro circuit block and the output of the signal distribution network;
wherein the plurality of configurable delay circuits comprises at least a first configurable delay circuit and a second configurable delay circuit, which have a same footprint, but have different delay characteristics.
13 . The integrated circuit of claim 12 , wherein the signal distribution network is a clock signal distribution network, and wherein the input of the macro circuit block is a clock input.
14 . The integrated circuit of claim 12 , wherein the signal distribution network is a data signal distribution network, and wherein the input of the macro circuit block is a data input.
15 . The integrated circuit of claim 12 , wherein the first and second configurable delay circuits each comprise a chain of buffers, wherein a number of buffers in the chain of buffers is the same in the first and second configurable delay circuits.
16 . The integrated circuit of claim 15 , wherein a total delay for a given one of the first and second configurable delay circuits is based on a number of buffers in the chain of buffers, which are serially connected between an input and output of the given configurable delay circuit.
17 . The integrated circuit of claim 12 , wherein the chain of configurable delay circuits further comprises a third configurable delay circuit having footprint that is different than the footprints of the first and second configurable delay circuits.
18 . A chip package comprising the integrated circuit of claim 12 .
19 . An integrated circuit, comprising:
a macro circuit block having an input;
a signal distribution network having an output; and
a chain of configurable delay circuits serially connected between the input of the macro circuit block and the output of the signal distribution network;
wherein the plurality of configurable delay circuits comprises at least a first configurable delay circuit and a second configurable delay circuit, which have different footprints, but have the same delay characteristics.
20 . A chip package comprising the integrated circuit of claim 19 .