Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
View Patent ↗A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.
1. A method of a chip-level implementation process, comprising:
filling un-wired tracks of each core logic in a chip with grounded metal;
filling un-wired tracks of a chip-level routing layer adjacent to an outermost layer of the each core logic with the grounded metal in a direction orthogonal to a preferred direction of the un-wired tracks in the outermost layer of the each core logic;
constraining the grounded metal of the chip-level routing layer to be within a planar area of a core window along the chip-level routing layer that exactly corresponds in size to a planar area along the outermost layer of the each core logic comprising the grounded metal thereof; and
generating, through a processor, a core timing model of the each core logic in the chip following the filling of the un-wired tracks of the each core logic and the un-wired tracks of the chip-level routing layer and the constraining of the grounded metal of the chip-level routing layer.
2. The method of claim 1 , further comprising performing an over-core chip-level routing of the chip-level routing layer in the chip-level implementation process.
3. The method of claim 1 , wherein the filled metal in the chip-level routing layer has physical characteristics typical for the layer.
4. The method of claim 3 , wherein the filled metal in the chip-level routing layer represents a similar parasitic characteristic to the each core logic during the generation of the core timing model.
5. The method of claim 1 , further comprising using the core timing model of the each logic to perform timing analysis during the chip-level implementation process.
6. The method of claim 1 , further comprising applying the core timing model to generate one of a delay model and a cross-talk immune model of a hierarchical structure independent of logic type.