Unified layer stack architecture
View Patent ↗A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.
1. A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design, the method comprising the steps of:
producing the highest level design,
in a programmed computing system without user intervention,
automatically processing the highest level design to selectively remove at least one predetermined metal layer, and
automatically mapping a closest remaining overlying layer to the at least one removed metal layer to a closest remaining underlying layer to the at least one removed metal layer,
thereby producing the at least one lower level design.
2. The method of claim 1 , wherein the highest level design is produced in a CAD tool.
3. The method of claim 1 , wherein the highest level design is processed in an internal file format.
4. The method of claim 1 , wherein the highest level design is processed in an external file format.
5. The method of claim 1 , wherein the at least one lower level design is produced in an internal file format.
6. The method of claim 1 , wherein the at least one lower level design is produced in an external file format.
7. The method of claim 1 , wherein the at least one removed metal layer includes only power routing and ground routing and does not include any signal routing.
8. The method of claim 1 , wherein the highest level design includes exactly seven bottom metal layers and exactly two top metal layers.
9. The method of claim 1 , wherein no more than one top metal layer from the highest level design is removed.
10. The method of claim 1 , wherein no more than two bottom metal layers from the highest level design are removed.
11. The method of claim 1 , wherein the programmed computing system is the CAD tool.
12. The method of claim 1 , wherein the programmed computing system is a DRC tool.
13. The method of claim 1 , wherein the programmed computing system is a LVS tool.
14. The method of claim 1 , wherein a plurality of lower level designs is produced by selectively removing a different number of predetermined metal layers from the highest level design to produce each of the plurality of lower level designs.
15. The method of claim 1 , wherein the highest level design is a 7+2 TSMC design and the at least one lower level design is at least one of a 7+1, 6+2, 6+1, 5+2, and 5+1 TSMC design.
16. The method of claim 1 , wherein the first five metal layers are identical between the highest level design and the at least one lower level design.
17. A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design, the method comprising the steps of:
producing the highest level design to include seven bottom metal layers and two top metal layers,
in a programmed computing system without user intervention,
automatically processing the highest level design to selectively remove at least one predetermined metal layer, where the at least one predetermined metal layer is selected from the group consisting essentially of no more than both of an upper two of the seven bottom metal layers and no more than one of the two top metal layers, and
automatically mapping a closest remaining overlying layer to the at least one removed metal layer to a closest remaining underlying layer to the at least one removed metal layer,
thereby producing the at least one lower level design.
18. The method of claim 17 , wherein the at least one removed metal layer includes only power routing and ground routing and does not include any signal routing.
19. The method of claim 17 , wherein the at least one lower level design includes all of a 7+1, 6+2, 6+1, 5+2, and 5+1 TSMC design.
20. A computing apparatus for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design, the computing apparatus comprising:
an input adapted to receive the highest level design,
a processor adapted to,
selectively remove at least one predetermined metal layer from the highest level design, and
map a closest remaining overlying layer to the at least one removed metal layer to a closest remaining underlying layer to the at least one removed metal layer, and
an output adapted to provide the at least one lower level design.