Circuits and methods for efficient clock and data delay configuration for faster timing closure
View Patent ↗Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps.
1. A method of designing an integrated circuit, comprising:
performing a logical synthesis process to generate a gate level representation of an integrated circuit design using one or more component cells selected from a cell library, wherein the selected component cells included in the gate level representation of the integrated circuit design include macro cells and configurable delay cell circuits;
performing a placement process to place a configurable delay cell circuit in proximity to a macro cell in the integrated circuit design;
performing a signal distribution network synthesis process to build a signal distribution network that is connected to an input of the configurable delay cell circuit in the integrated circuit design;
performing a routing process to add wiring to the integrated circuit design;
performing a timing analysis to determine if timing constraints for the integrated circuit design are satisfied;
when a given timing constraint is not satisfied, replacing the configurable delay cell circuit in the integrated circuit design with a new configurable delay cell circuit which has a same footprint as the replaced configurable delay cell circuit, but which has a different delay characteristic that is selected to meet the given timing constraint; and
repeating the timing analysis with the new configurable delay cell circuit, wherein the timing analysis is repeated without having to repeat the placement, signal distribution network synthesis, and routing processes,
wherein the logical synthesis, placement, signal distribution network synthesis, routing and timing analysis processes are performed using a computer.
2. The method of claim 1 , wherein performing a placement process comprises placing an output pin of the configurable delay cell circuit in proximity to an input pin of the macro cell.
3. The method of claim 2 , wherein the signal distribution network comprises a clock signal distribution network, and wherein the input pin of the macro cell is a clock input pin.
4. The method of claim 2 , wherein the signal distribution network comprises a data signal distribution network, and wherein the input pin of the macro cell is a data input pin.
5. The method of claim 1 , wherein performing a signal distribution network synthesis process comprises considering a delay characteristic of the configurable delay cell circuit that is to be connected to the output of the signal distribution network.
6. The method of claim 1 , wherein performing a placement process comprises placing two or more serially connected configurable delay cell circuits in proximity to a macro cell in the integrated circuit design.
7. The method of claim 1 , wherein the cell library comprises one or more sets of configurable delay cell circuits, wherein each configurable delay cell circuit in a given set of configurable delay cell circuits has a same footprint and a different delay characteristic.
8. The method of claim 7 , wherein the footprints of configurable delay cell circuits of different sets of configurable delay cell circuits are different.
9. The method of claim 7 , wherein each configurable delay cell circuit in a given set of configurable delay cell circuits comprises a chain of buffers, wherein a number of buffers in the chain of buffers is the same for each configurable delay cell circuit in the given set.
10. The method of claim 9 , wherein a total delay for a given configurable delay cell circuit is based on a number of buffers in the chain of buffers, which are serially connected between an input port and an output port of the given configurable delay cell circuit.
11. A computer readable storage medium comprising a program of instructions which, when executed by a computer, perform the method steps of claim 1 for designing an integrated circuit.
12. A computing system, comprising:
a memory to store program instructions for designing an integrated circuit and to store a cell library comprising a plurality of component cells, wherein the component cells include macro cells and configurable delay cell circuits;
a processor system coupled to the memory, wherein the processor system is operative to execute the stored program instructions to perform a method for designing an integrated circuit, the method comprising:
performing a logical synthesis process to generate a gate level representation of an integrated circuit design using one or more component cells selected from a cell library, wherein the selected component cells included in the gate level representation of the integrated circuit design include macro cells and configurable delay cell circuits,
performing a placement process to place a configurable delay cell circuit in proximity to a macro cell in the integrated circuit design;
performing a signal distribution network synthesis process to build a signal distribution network that is connected to an input of the configurable delay cell circuit in the integrated circuit design;
performing a routing process to add wiring to the integrated circuit design;
performing a timing analysis to determine if timing constraints for the IC design are satisfied;
when a given timing constraint is not satisfied, replacing the configurable delay cell circuit in the IC design with a new configurable delay cell circuit which has a same footprint as the replaced configurable delay cell circuit, but which has a different delay characteristic that is selected to meet the given timing constraint; and
repeating the timing analysis with the new configurable delay cell circuit, wherein the timing analysis is repeated without having to repeat the placement, signal distribution network synthesis, and routing processes.
13. The computing system of claim 12 , wherein in performing a placement process, the processor system is operative to place an output pin of the configurable delay cell circuit in proximity to an input pin of the macro cell.
14. The computing system of claim 13 , wherein the signal distribution network comprises a clock signal distribution network, and wherein the input pin of the macro cell is a clock input pin.
15. The computing system of claim 13 , wherein the signal distribution network comprises a data signal distribution network, and wherein the input pin of the macro cell is a data input pin.
16. The computing system of claim 12 , wherein in performing a signal distribution network synthesis process, the processor system is operative to consider a delay characteristic of the configurable delay cell circuit that is to be connected to the output of the signal distribution network.
17. The computing system of claim 12 , wherein in performing a placement process, the processor system is operative to place two or more serially connected configurable delay cell circuits in proximity to a macro cell in the IC design.
18. The computing system of claim 12 , wherein the cell library comprises one or more sets of configurable delay cell circuits, wherein each configurable delay cell circuit in a given set of configurable delay cell circuits has a same footprint and a different delay characteristic.
19. The computing system of claim 18 , wherein the footprints of configurable delay cell circuits of different sets of configurable delay cell circuits are different.
20. The computing system of claim 18 , wherein each configurable delay cell circuit in a given set of configurable delay cell circuits comprises a chain of buffers, wherein a number of buffers in the chain of buffers is the same for each configurable delay cell circuit in the given set.
21. The computing system of claim 20 , wherein a total delay for a given configurable delay cell circuit is based on a number of buffers in the chain of buffers, which are serially connected between an input port and an output port of the given configurable delay cell circuit.