Timing signoff system and method that takes static and dynamic voltage drop into account
View Patent ↗A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply.
1. A system for performing static timing analysis, comprising:
a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design; and
an STA tool configured to derate a timing of said each of said cells based on said corresponding cell-based voltage supply;
wherein said tools are embodied in program code stored in a non-transitory computer readable storage medium, said program code executed by a computer.
2. The system as recited in claim 1 wherein said STA tool is further configured to derate said each of said cells based on a sensitivity of a delay of said each of said cells to a change in said corresponding cell-based voltage supply.
3. The system as recited in claim 1 wherein said STA tool is further configured to derate said each of said cells based on a voltage used in a delay library for a particular signoff corner.
4. The system as recited in claim 1 wherein said STA tool is further configured to derate said each of said cells based on real voltage variations.
5. The system as recited in claim 1 wherein said STA tool is further configured to derate said each of said cells based on reduced on-chip variation margins.
6. The system as recited in claim 1 further comprising a script executable to cause said STA tool to derate said each of said cells, said script including at least one statement defining a derating factor.
7. The system as recited in claim 1 wherein said integrated circuit design employs adaptive voltage scaling.
8. A method of performing static timing analysis, comprising:
determining a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design; and
derating a timing of said each of said cells based on said corresponding cell-based voltage supply;
wherein said method is executable by a computer.
9. The method as recited in claim 8 wherein said derating comprises derating said each of said cells based on a sensitivity of a delay of said each of said cells to a change in said corresponding cell-based voltage supply.
10. The method as recited in claim 8 wherein said derating comprises derating said each of said cells based on a voltage used in a delay library for a particular signoff corner.
11. The method as recited in claim 8 wherein said derating comprises derating said each of said cells based on real voltage variations.
12. The method as recited in claim 8 wherein said derating comprises derating said each of said cells based on reduced on-chip variation margins.
13. The method as recited in claim 8 further comprising executing a script to carry out said derating of said each of said cells, said script including at least one statement defining a derating factor.
14. The method as recited in claim 8 wherein said integrated circuit design employs adaptive voltage scaling.
15. A design process optimization system for designing an integrated circuit employing adaptive voltage scaling, comprising:
a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design;
process-voltage-temperature (PVT) libraries configured to contain PVT libraries of PVT characterizations; and
an STA tool configured to calculate a delay corresponding to each of said cells based on one of said PVT libraries and derate a timing of said each of said cells based on said corresponding delay and said corresponding cell-based voltage supply;
wherein said tools are embodied in program code stored in a non-transitory computer readable storage medium, said program code executed by a computer.
16. The system as recited in claim 15 wherein said STA tool is further configured to derate said each of said cells based on a sensitivity of a delay of said each of said cells to a change in said corresponding cell-based voltage supply.
17. The system as recited in claim 15 wherein said STA tool is further configured to derate said each of said cells based on a voltage used in a delay library for a particular signoff corner.
18. The system as recited in claim 15 wherein said STA tool is further configured to derate said each of said cells based on real voltage variations.
19. The system as recited in claim 15 further comprising a script executable to cause said STA tool to derate said each of said cells, said script including at least one statement defining a derating factor.
20. The system as recited in claim 15 wherein said STA tool is further configured to derate said each of said cells based on reduced on-chip variation margins.