Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same
View Patent ↗A method of manufacturing an electronic circuit employing a flexible ramptime limit and an electronic circuit are disclosed. In one embodiment, the method includes: (1) physically synthesizing a logical representation of an electronic circuit employing flexible ramptime limits, (2) performing a timing test on the physically synthesized electronic circuit employing the flexible ramptime limits and a processor and (3) determining if there is a violation of the flexible ramptime limits.
1. A method of manufacturing an electronic circuit, comprising:
physically synthesizing a logical representation of an electronic circuit employing flexible ramptime limits, wherein a flexible ramptime limit is a minimum ramptime limit between a frequency based ramptime limit and a library based ramptime limit associated with said electronic circuit;
performing a timing test on said physically synthesized electronic circuit employing said flexible ramptime limits and a processor; and
determining if there is a violation of said flexible ramptime limits.
2. The method as recited in claim 1 further comprising waiving or correcting said violation if present.
3. The method as recited in claim 2 further comprising repeating said performing and said determining after correcting said violation.
4. The method as recited in claim 3 further comprising manufacturing an electronic circuit based on said physically synthesized electronic circuit after checking for ramptime violations.
5. The method as recited in claim 1 further comprising manufacturing an electronic circuit based on said physically synthesized electronic circuit after determining if there is a violation of said flexible ramptime limits.
6. The method as recited in claim 1 wherein said determining is based on said timing test.
7. The method as recited in claim 1 wherein said frequency based ramptime limit is calculated for each data signal and clock signal of said electronic circuit.
8. The method as recited in claim 1 wherein said library based ramptime limit is obtained for each data signal and clock signal of said electronic circuit.
9. The method as recited in claim 1 further comprising automatically determining said flexible ramptime limit based on said frequency based ramptime limit and said library based ramptime limit.
10. The method as recited in claim 1 wherein said flexible ramptime limits include a flexible ramptime limit of a data net of said electronic circuit and a flexible ramptime limit of a clock net of said electronic circuit.
11. The method as recited in claim 1 wherein said flexible ramptime limits include a flexible ramptime limit for each data net of said electronic circuit and a flexible ramptime limit for each clock net of said electronic circuit.
12. The method as recited in claim 1 wherein said physically synthesizing includes placement and routing stages.
13. The method as recited in claim 1 wherein said physically synthesizing is performed by a first electronic design automation tool and said performing a timing test is performed by a second electronic design automation tool.
14. An electronic circuit manufactured according to a method comprising:
physically synthesizing a logical representation of said electronic circuit employing flexible ramptime limits, wherein a flexible ramptime limit is a minimum ramptime limit between a frequency based ramptime limit and a library based ramptime limit associated with said electronic circuit;
performing a timing test on said physically synthesized electronic circuit employing said flexible ramptime limits and a processor; and
determining if there is a violation of said flexible ramptime limits.