Circuit timing analysis incorporating the effects of temperature inversion
Methods and apparatus for increasing the accuracy of timing characterization of a circuit including one or more cells in a cell library are provided. One method includes the steps of: performing cell library timing characterization for each of the cells in the circuit for at least first and second prescribed temperatures, the first and second temperatures corresponding to first and second PVT corners, respectively, in the cell library; calculating respective cell delays for the one or more cells in the circuit, the cell delay calculation being a function of temperature for each instance of the one or more cells; and incorporating the cell delay calculation into the timing characterization for each of the cells in the circuit to thereby increase the accuracy of the timing characterization.
1. A computer-implemented method for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the method comprising the steps of:
performing cell library timing characterization for the at least one cell in the circuit for at least first and second prescribed temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively, the first and second temperatures corresponding to first and second process, voltage and temperature (PVT) corners, respectively, in the cell library;
for each instance of the at least one cell in the circuit, determining at least one of a third temperature at which cell delay is maximum and a fourth temperature at which cell delay is minimum, the third and fourth temperatures being between the first and second temperatures;
performing cell library timing characterization for the at least one cell in the circuit using at least one of the third and fourth temperatures;
calculating a cell delay for the at least one cell, the cell delay calculation being a function of at least one of the third and fourth temperatures for each instance of the at least one cell in the circuit; and
incorporating the cell delay calculation into the timing characterization for the at least one cell in the circuit to take into account effects of temperature inversion and thereby increase the accuracy of the timing characterization, wherein the steps are performed at least in part by a processor.
2. The method of claim 1 , wherein the step of calculating the cell delay comprises:
determining a temperature map corresponding to a physical layout of the at least one cell in the circuit; and
determining the cell delay of the at least one cell as a function of a temperature at a physical location of the at least one cell.
3. The method of claim 2 , wherein the step of calculating the cell delay further comprises:
determining a first delay of the at least one cell at the first prescribed temperature;
determining a second delay of the at least one cell at the second prescribed temperature; and
interpolating between the first and second delays to determine the cell delay of the at least one cell at the temperature at the physical location of the cell.
4. The method of claim 3 , wherein the step of interpolating comprises scaling the first and second delays corresponding to the first and second PVT corners, respectively, in the cell library.
5. The method of claim 1 , wherein the step of incorporating the cell delay calculation into the timing characterization for the at least one cell comprises modifying at least one parameter of the timing characterization for the at least one cell in the circuit.
6. The method of claim 1 , wherein the step of performing cell library timing characterization comprises simulating delay values for the at least one cell at each of the PVT corners in the cell library using at least one of a static timing analysis tool and a statistical static timing analysis tool.
7. The method of claim 1 , wherein the step of performing cell library timing characterization comprises determining all critical timing paths in the circuit.
8. Apparatus for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the apparatus comprising:
memory; and
at least one processor coupled to the memory, the at least one processor being operative: (i) to perform cell library timing characterization for the at least one cell in the circuit for at least first and second prescribed temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively, the first and second temperatures corresponding to first and second process, voltage and temperature (PVT) corners, respectively, in the cell library; (ii) for each instance of the at least one cell, to determine at least one of a third temperature at which cell delay is maximum and a fourth temperature at which cell delay is minimum, the third and fourth temperatures being between the first and second temperatures; (iii) to perform cell library timing characterization for the at least one cell in the circuit using at least one of the third and fourth temperatures; (iv) to calculate a cell delay for the at least one cell in the circuit, the cell delay calculation being a function of at least one of the third and fourth temperatures for each instance of the at least one cell; and (v) to incorporate the cell delay calculation into the timing characterization for the at least one cell in the circuit to take into account effects of temperature inversion and thereby increase the accuracy of the timing characterization.
9. The apparatus of claim 8 , wherein the at least one process is further operative: to determine a temperature map corresponding to a physical layout of the at least one cell in the circuit; and to determine the cell delay of the at least one cell as a function of a temperature at a physical location of the at least one cell.
10. The apparatus of claim 9 , wherein the at least one process is further operative: to determine a first delay of the at least one cell at the first prescribed temperature; to determine a second delay of the at least one cell at the second prescribed temperature; and to interpolate between the first and second delays to determine the cell delay of the at least one cell at the temperature at the physical location of the cell.
11. The apparatus of claim 10 , wherein the at least one process is further operative to scale the first and second delays corresponding to the first and second PVT corners, respectively, in the cell library.
12. The apparatus of claim 8 , wherein the at least one process is further operative to modify at least one parameter of the timing characterization for the at least one cell in the circuit.
13. The apparatus of claim 8 , wherein the at least one process is further operative to determining all critical timing paths in the circuit.