IP Library Granted Patent US 8,151,237
Granted Patent B2
US 8,151,237 · App. 12/229,446 · Granted Apr 3, 2012

Disabling unused IO resources in platform-based integrated circuits

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Quick Facts
Patent No.
US 8,151,237
App. No.
12/229,446
Granted
Apr 3, 2012
Kind
B2
Abstract

The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.

Claims (33)

1. A method for converting unused IO resources to a disabled state in a platform-based integrated circuit, comprising steps of:

receiving a slice including an IO circuit from a vendor, said IO circuit being unused by a customer;

disabling said IO circuit;

removing said IO circuit from a logic design netlist of said customer; and

inserting said IO circuit in a physical design database of said vendor.

2. The method of claim 1 , wherein said disabling step comprises when said IO circuit is desired to be tied to a power source, shorting a primary input/output pin of said IO circuit to a power bus of said IO circuit.

3. The method of claim 2 , wherein said shorting occurs via a bonding pad cell of said slice, said bonding pad cell being connected to said primary input/output pin and said power bus.

4. The method of claim 3 , wherein said power bus is on an uppermost metal layer of said IO circuit.

5. The method of claim 4 , wherein said primary input/output pin is on a metal layer of said IO circuit, said metal layer being not said uppermost metal layer of said IO circuit.

6. The method of claim 5 , wherein an uppermost metal layer of said bonding pad cell is connected to said power bus, and a metal layer of said bonding pad cell is connected to said primary input/output pin, said metal layer of said bonding pad cell being not said uppermost metal layer of said bonding pad cell.

7. The method of claim 2 , wherein said shorting occurs by connecting, inside said IO circuit, said primary input/output pin to said power bus without using a bonding pad cell of said slice.

8. The method of claim 1 , wherein said disabling step comprises when said IO circuit is desired to be tied to a ground source, shorting a primary input/output pin of said IO circuit to a ground bus of said IO circuit.

9. The method of claim 8 , wherein said shorting occurs via a bonding pad cell of said slice, said bonding pad cell being connected to said primary input/output pin and said ground bus.

10. The method of claim 9 , wherein said ground bus is on an uppermost metal layer of said IO circuit.

11. The method of claim 10 , wherein said primary input/output pin is on a metal layer of said IO circuit , said metal layer being not said uppermost metal layer of said IO circuit.

12. The method of claim 11 , wherein an uppermost metal layer of said bonding pad cell is connected to said ground bus, and a metal layer of said bonding pad cell is connected to said primary input/output pin, said metal layer of said bonding pad cell being not said uppermost metal layer of said bonding pad cell.

13. The method of claim 8 , wherein said shorting occurs by connecting, inside said IO circuit, said primary input/output pin to said ground bus without using a bonding pad cell of said slice.

14. The method of claim 1 , wherein said disabling step comprises when said IO circuit is desired to be left floated, keeping a primary input/output pin of said IO circuit unconnected to any bonding pad cell of said slice.

15. The method of claim 1 , wherein said disabling step comprises when said IO circuit is desired to be left floated and when said slice is packaged in wirebond packaging, removing a bonding wire corresponding to said IO circuit.

16. The method of claim 1 , wherein said disabling step comprises when said IO circuit is desired to be left floated and when said slice is packaged in flipchip packaging, removing a flip chip bump corresponding to said IO circuit.

17. A tangible, non-transitory, computer usable medium having computer-executable instructions for performing a method for converting unused IO resources to a disabled state in a platform-based integrated circuit, said method comprising steps of:

receiving a slice including an IO circuit from a vendor, said IO circuit being unused by a customer;

disabling said IO circuit;

removing said IO circuit from a logic design netlist of said customer; and

inserting said IO circuit in a physical design database of said vendor.

18. The tangible, non-transitory, computer useable medium of claim 17 , wherein said disabling step comprises when said IO circuit is desired to be tied to a power source, shorting a primary input/output pin of said IO circuit to a power bus of said IO circuit.

19. The tangible, non-transitory, computer usable medium of claim 17 , wherein said disabling step comprises when said IO circuit is desired to be tied to a ground source, shorting a primary input/output pin of said IO circuit to a ground bus of said IO circuit.

20. The tangible, non-transitory, computer useable medium of claim 17 , wherein said disabling step comprises when said IO circuit is desired to be left floated, keeping a primary input/output pin of said IO circuit unconnected to any bonding pad cell of said slice.

21. A method for converting unused IO resources to a disabled state in a platform-based integrated circuit, comprising steps of:

receiving a slice including an IO circuit from a vendor, said IO circuit being unused by a customer;

connecting said IO circuit to a fixed voltage in a region of said slice;

removing said IO circuit from a logic design netlist of said customer; and

inserting said IO circuit in a physical design database of said vendor.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →