IP Library Granted Patent US 7,640,152
Granted Patent B2
US 7,640,152 · App. 12/150,846 · Granted Dec 29, 2009

Accurate pin-based memory power model using arc-based characterization

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Quick Facts
Patent No.
US 7,640,152
App. No.
12/150,846
Granted
Dec 29, 2009
Kind
B2
Abstract

A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value.

Claims (22)

1. A computer-readable medium having computer-executable instructions for performing a pin-based memory power dissipation determination method using arc-based characterization, said pin-based memory power modeling method comprising steps of:

detecting a number of switching data output pins of a memory as n, said memory including m data output pins; and

computing Write power for a power arc from a clock pin of said memory to a data output pin of said memory when said clock pin switches, a write enable signal of said memory is high, and said n data output pins of said memory switch, comprising:

for said clock pin, providing first current consumption when said clock pin switches, said write enable signal is high, no data input pin of said memory switches, and none of said m data output pins of said memory switches;

for said data output pin, providing second current consumption when said clock pin switches, said write enable signal is high, all data input pins of said memory switch, and all said m data output pins of said memory switch;

calculating third current consumption caused by switching of said all said m data output pins of said memory as: said third current consumption=said second current consumption−said first current consumption; and

calculating said Write power as: said Write power=said first current consumption+said third current consumption*(said n/said in),

utilizing said Write power to determine a silicon power dissipation for said memory.

2. The computer-readable medium of claim 1 , wherein said step of detecting is implemented by a power estimation tool based on simulation.

3. The computer-readable medium of claim 1 , wherein said step of computing Write power further comprises obtaining said first current consumption from a clock pin Write power table by a power estimation tool.

4. The computer-readable medium of claim 1 , wherein said pin-based memory power dissipation determination method further comprises a step of:

computing Read power for said power arc when said clock pin switches, said write enable signal of said memory is low, and said n data output pins of said memory switch, comprising:

for said clock pin, providing fourth current consumption when said clock pin switches, said write enable signal is low, and none of said m data output pins of said memory switches;

for said data output pin, providing fifth current consumption when said clock pin switches, said write enable signal is low, and said all said m data output pins of said memory switch;

calculating sixth current consumption caused by switching of said all said m data output pins of said memory as: said sixth current consumption=said fifth current consumption−said fourth current consumption; and

calculating said Read power as: said Read power=said fourth current consumption+said sixth current consumption*(said n/said in).

5. The computer-readable medium of claim 4 , wherein said step of computing Read power further comprises obtaining said fourth current consumption from a clock pin Read power table by a power estimation tool.

6. The computer-readable medium of claim 1 , wherein said pin-based memory power dissipation determination method further comprises a step of:

computing a second Write power for a second power arc from a pin of said memory to a data output pin of said memory when said pin switches, a write enable signal of said memory is high, and said n data output pins of said memory switch,

wherein said pin is an address pin or a data input pin of said memory.

7. The computer-readable medium of claim 6 , wherein said pin-based memory power dissipation determination method further comprises a step of:

computing a second Read power for said second power arc when said pin switches, said write enable signal of said memory is low, and said n data output pins of said memory switch.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →