Granted Patent B2

US 8,006,209 · App. 12/315,998 · Granted Aug 23, 2011

Assignee: LSI Corporation

Abstract

Claims (26)

1. A method for constructing a processor for outputting a sequence of commands and data described by a flowchart, comprising:

diffusing a processor in a slice, said processor including a ROM;

connecting said processor to a RRAM controller in said slice;

receiving a flowchart describing a sequence of commands and data, said flowchart including a plurality of flowchart symbols of an integrated circuit;

assigning ROM records to said plurality of flowchart symbols;

storing said ROM records in said ROM;

outputting, by said processor, said sequence of commands and data to said RRAM controller for managing a process of testing and self-repairing memories of RRAMs, said RRAMs being communicatively coupled to said RRAM controller.

2. A system for outputting a sequence of commands and data described by a flowchart, comprising:

a ROM for storing ROM records, said ROM records being assigned to flowchart symbols of an integrated circuit, said flowchart symbols being included in a flowchart describing a sequence of commands and data;

a logic module PROCESSOR_CONTROL, communicatively coupled to said ROM, for receiving said ROM records from said ROM and outputting said sequence of commands and data, said logic module PROCESSOR_CONTROL including flipflops, said logic module PROCESSOR_CONTROL receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x 1 , x 2 , . . . x N ; and

a RRAM controller communicatively coupled to said logic module.

3. The system of claim 2 , wherein the RRAM controller is communicatively coupled to said logic module for providing said ENABLE signal and said N binary inputs x 1 , x 2 , . . . x N to said logic module PROCESSOR_CONTROL and for receiving said sequence of commands from said logic module PROCESSOR_CONTROL, wherein said RRAM controller manages a process of testing and self-repairing memories of RRAMs, said RRAMs being communicatively coupled to said RRAM controller.

4. The system of claim 2 , wherein said flowchart symbols include command and data, jump, optional jump, start, finish, start subflowchart, call subflowchart, and finish subflowchart.

5. The system of claim 4 , wherein said ROM records are assigned as follows:

1) for symbols start or start subflowchart: 000<command_value><data_value><next_input_index>;

2) for symbol simple command and data: 001<command_value><data_value><next_input_index>000;

3) for symbol optional command and data if(x i ): 001<command_value><data_value><next_input_index>001;

4) for symbol optional command and data if(!x i ): 001<command_value><data_value><next_input_index>002;

5) for symbol continuous command and data while(x i ): 001<command_value><data_value><next_input_index>003;

6) for symbol continuous command and data while(!x i ): 001<command_value><data_value><next_input_index>004;

7) for symbol jump: 002<command_value><data_value><next_input_index><jump_address>;

8) for symbol optional jump with condition if(x i ): 003<command_value><data_value><next_input_index><jump_address><jump_input_index>, where said <jump_input_index> is an <input_index> of a symbol to which jump is addressed;

9) for symbol optional jump with condition if(!x i ): 004<command_value><data_value><next_input_index><jump_address><jump_input_index>, where said <jump_input_index> is an <input_index> of a symbol to which jump is addressed;

10) for symbol call subflowchart: 005<command_value><data_value><next_input_index><address><jump_input_index>, where said <address> is an address of a symbol start subflowchart of a corresponding subflowchart, and said <jump_input_index> is an <input_index> of said symbol;

11) for symbol finish subflowchart: 006<command_value><data_value><next_input_index>; and

12) for symbol finish: 002<command_value><data_value><input_index><address><input_index>, where <address> is an address of said flowchart symbol finish.

Assignments (8)

Continuity (2)