Method for estimation of trace information bandwidth requirements
View Patent ↗A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning.
1. A method of having a computer program embodied on a computer readable medium evaluate the feasibility for proposed SoC architecture comprising the steps of:
having a user enter input variables relating to a proposed SoC architecture for generating and capturing trace information;
assigning values to the input variables;
generating trace information;
determining whether it is an appropriate time to place said trace information into a trace source FIFO;
if the time is appropriate, placing said trace information into said trace source FIFO;
determining whether it is an appropriate time to remove said trace information from said trace source FIFO;
if the time is appropriate, removing said trace information from said trace source FIFO;
capturing the level of data present in said trace source FIFO at various clock cycles;
analyzing the level of data present in said trace source FIFO at various clock cycles to determine the percentage of said trace source FIFO's maximum level occupied by said trace information; and
analyzing the percentages calculated to determine if the proposed architecture will accommodate said trace information.
2. The method of claim 1 , wherein said step of assigning values includes assigning a trace source FIFO size.
3. The method of claim 1 , wherein said step of assigning values includes assigning a trace sink FIFO size.
4. The method of claim 1 , wherein said step of assigning values includes assigning a Bits Per Instruction value.
5. The method of claim 1 , wherein said step of assigning values includes assigning a Bits Per Data value.
6. The method of claim 1 , wherein said step of assigning values further includes the step of defining the trace port width.
7. The method of claim 1 , wherein said step of removing said trace information from said trace source FIFO further includes providing said trace information at a trace port.
8. The method of claim 1 , wherein said step of assigning values further includes assigning the clock rate at which trace information is placed in and taken out of the trace source FIFO.
9. The method of claim 1 , wherein said step of assigning values includes assigning a threshold limit for data suppression.
10. The method of claim 3 , wherein said step of removing said trace information from said trace source FIFO further includes placing said trace information in a trace sink FIFO.
11. The method of claim 10 , further including the step of removing said trace information from said trace sink FIFO and providing said trace information at a trace port.
12. The method of claim 10 , wherein said step of assigning values includes assigning the clock rate at which trace information is placed in and taken out of the trace sink FIFO.
13. The method of claim 10 , further comprising the steps of:
capturing the level of data present in said trace sink FIFO at various clock cycles;
analyzing the level of data present in said trace sink FIFO at various clock cycles to determine the percentage of said trace sink FIFO's maximum level occupied by the information; and
analyzing the percentages calculated to determine if the proposed architecture will accommodate said trace sink information.
14. A method of evaluating a proposed trace architecture in a SoC comprising the steps of:
proposing a trace architecture;
providing a computer program embodied on a computer readable medium to accept input variables from a user relating to said trace architecture;
having a user enter said input variables into said computer program;
executing said computer program to generate results about the proposed trace architecture; and, without requiring hardware or firmware,
evaluating the results generated to determine if the proposed trace architecture is feasible, wherein said results include trace source FIFO information.
15. The method of claim 14 , wherein said input variables include the amount of trace information to be put into the trace source FIFO and the frequency at which the trace information is to be put into the trace source FIFO.
16. The method of claim 15 , wherein an estimated amount of trace information to be put into the trace source FIFO is provided through published documentation regarding the trace source.
17. The method of claim 15 , wherein an estimated amount of data to be put into the trace source FIFO is provided by running example software to provide the number of bits for each type of trace information.
18. The method of claim 14 , wherein said trace source FIFO information includes the number of instances wherein the trace source FIFO was full or overflows.
19. The method of claim 14 , wherein said trace source FIFO information includes the number of instances wherein data was suppressed by the trace source FIFO.
20. The method of claim 14 , wherein said trace source FIFO information includes the maximum level of data which occurred in the trace source FIFO.
21. The method of claim 14 , wherein said trace source FIFO information includes the amount of data traced in a predetermined number of clock cycles.
22. The method of claim 14 , wherein said results include trace sink FIFO information.
23. The method of claim 22 , wherein said trace sink FIFO information includes the number of instances wherein the trace sink FIFO was full or overflows.
24. The method of claim 22 , wherein said trace sink FIFO information includes the maximum level of data which occurred in the trace sink FIFO.
25. The method of claim 22 , wherein said trace sink FIFO information includes the amount of data traced in a predetermined number of clock cycles.
26. The method of claim 14 , wherein said input variables include the clock rate at which the trace information is placed in and taken out of the trace source FIFO.
27. The method of claim 14 , wherein said input variables include the clock rate at which the trace information is placed in and taken out of the trace sink FIFO.
28. The method of claim 14 , wherein said input variables include the type of trace information to be collected.
29. The method of claim 14 , wherein said input variables include a threshold limit for data suppression.
30. The method of claim 14 , wherein said input variables include an indication of the trace architecture as full or standalone.
31. The method of claim 14 , wherein said input variables include the trace source FIFO size and the trace sink FIFO size.
32. The method of claim 14 , wherein said input variables include the width of the trace port.